參數(shù)資料
型號(hào): ADSP-BF561SKBCZ600
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: Blackfin Embedded Symmetric Multi-Processor
中文描述: 32-BIT, 133 MHz, OTHER DSP, PBGA256
封裝: 12 X 12 MM, LEAD FREE, MO-225, MBGA-256
文件頁數(shù): 23/52頁
文件大?。?/td> 508K
代理商: ADSP-BF561SKBCZ600
ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 23 of 52
|
April 2004
Clock and Reset Timing
Table 13
and
Figure 7
describe clock and reset operations. Per
Figure 7
, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of 600/133 MHz.
Table 13. Clock and Reset Timing
Parameter
Timing Requirement
s
t
CKIN
t
CKINL
t
CKINH
t
WRST
Switching Characteristics
t
SCLK
1
Applies to bypass mode and non-bypass mode.
2
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
3
The figure below shows a x2 ratio between t
CKIN
and t
SCLK
, but the ratio has many programmable options. For more information, see the System Design chapter of the
ADSP-
BF561 Hardware Reference
.
4
t
SCLK
must always also be larger than t
C
C
LK
.
Min
Max
Unit
CLKIN Period
CLKIN Low Pulse
1
CLKIN High Pulse
1
RESET Asserted Pulsewidth Low
2
25.0
10.0
10.0
11t
CKIN
100.0
ns
ns
ns
ns
CLKOUT Period
3
7.5
4
ns
Figure 7. Clock and Reset Timing
t
SCLKD
CLKOUT
RESET
CLKIN
t
CKINH
t
CKIN
t
CKINL
t
SCLK
t
WRST
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