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參數(shù)資料
| 型號： | ADSP-BF561SKBCZ500 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Blackfin Embedded Symmetric Multi-Processor |
| 中文描述： | 32-BIT, 500 MHz, OTHER DSP, PBGA256 |
| 封裝： | 12 X 12 MM, ROHS COMPLIANT, MO-225, BGA-256 |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 508K |
| 代理商： | ADSP-BF561SKBCZ500 |
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Rev. PrC
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Page 10 of 52
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April 2004
ADSP-BF561
Preliminary Technical Data
The capabilities of UART0 are further extended with support
for the InfraRed Data Association (IrDA) Serial InfraRed Phys-
ical Layer Link Specification (SIR) protocol.
PROGRAMMABLE FLAGS (PFX)
The ADSP-BF561 has 48 bi-directional, general-purpose I/O,
Programmable Flag (PF47–0) pins. The Programmable Flag
pins have special functions for SPI port operation. Each pro-
grammable flag can be individually controlled as follows by
manipulation of the flag control, status, and interrupt registers:
Flag Direction Control Register – Specifies the direction of
each individual PFx pin as input or output.
Flag Control and Status Registers – Rather than forcing the
software to use a read-modify-write process to control the
setting of individual flags, the ADSP-BF561 employs a
"write one to set" and "write one to clear" mechanism that
allows any combination of individual flags to be set or
cleared in a single instruction, without affecting the level of
any other flags. Two control registers are provided, one
register is written to in order to set flag values while
another register is written to in order to clear flag values.
Reading the flag status register allows software to interro-
gate the sense of the flags.
Flag Interrupt Mask Registers – The Flag Interrupt Mask
Registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the Flag Control Reg-
isters that are used to set and clear individual flag values,
one Flag Interrupt Mask Register sets bits to enable inter-
rupt function, and the other Flag Interrupt Mask register
clears bits to disable interrupt function. PFx pins defined as
inputs can be configured to generate hardware interrupts,
while output PFx pins can be configured to generate soft-
ware interrupts.
Flag Interrupt Sensitivity Registers – The Flag Interrupt
Sensitivity Registers specify whether individual PFx pins
are level- or edge-sensitive and specify-if edge-sensitive-
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
TIMERS
There are fourteen (14) programmable timer units in the ADSP-
BF561. Twelve general-purpose timers have an external pin that
can be configured either as a Pulse Width Modulator (PWM) or
timer output, as an input to lock the timer, or for measuring
pulse widths of external events. Each of the twelve general-pur-
pose timer units can be independently programmed as a PWM,
internally or externally clocked timer, or pulse width counter.
The general-purpose timer units can be used in conjunction
with the UART to measure the width of the pulses in the data
stream to provide an auto-baud detect function for a serial
channel.
The general-purpose timers can generate interrupts to the pro-
cessor core providing periodic events for synchronization,
either to the processor clock or to a count of external signals. In
addition to the twelve general-purpose programmable timers,
another timer is also provided for each core. These extra timers
are clocked by the internal processor clock (CCLK) and is typi-
cally used as a system tick clock for generation of operating
system periodic interrupts.
PARALLEL PERIPHERAL INTERFACE
The processor provides two Parallel Peripheral Interfaces (PPI)
that can connect directly to parallel A/D and D/A converters,
ITU-R-601/656 video encoders and decoders, and other general
purpose peripherals. Each PPI consists of a dedicated input
clock pin, up to 3 frame synchronization pins, and up to 16 data
pins.
In ITU-R 656 mode, the PPI receives and parses a data stream of
8- bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
General Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
Data Receive with Internally Generated Frame Syncs.
Data Receive with Externally Generated Frame Syncs.
Data Transmit with Internally Generated Frame Syncs.
Data Transmit with Externally Generated Frame Syncs.
Input Mode
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception / transmission of data.
ITU -R 656 Mode Descriptions
Three distinct ITU-R 656 modes are supported:
Active Video Only Mode
Vertical Blanking Only Mode
Entire Field Mode
Active Video Only Mode
In this mode, the PPI does not read in any data between the End
of Active Video (EAV) and Start of Active Video (SAV) pream-
ble symbols, or any data present during the vertical blanking
intervals. In this mode, the control byte sequences are not stored
to memory; they are filtered by the PPI.
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data, as well as horizontal blanking information and con-
trol byte sequences on VBI lines.
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| ADSP-BF561SKBCZ600 | 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 600MHZ 600MIPS 256CSPBGA - Trays 制造商:Analog Devices 功能描述:IC MULTI-PROCESSOR |
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| ADSP-BF561SKBCZ-6A | 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
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