參數(shù)資料
型號(hào)： ADSP-21990BBC
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-bit fixed point DSP with Flash
中文描述： 16-BIT, 150 MHz, OTHER DSP, PBGA196
封裝： MINI, BGA-196
文件頁數(shù)： 17/44頁
文件大?。?/td> 574K
代理商： ADSP-21990BBC
–17–
REV. 0
ADSP-21990
SPECIFICATIONS
Specifications subject to change without notice.
RECOMMENDED OPERATING CONDITIONS—ADSP-21990BBC
Parameter
V
DDINT
V
DDEXT
AVDD
CCLK
HCLK
1, 2
CLKIN
3
T
JUNC
4
T
AMB
Min
2.375
3.135
2.375
0
0
0
Typ
2.5
3.3
2.5
Max
2.625
3.465
2.625
150
75
150
+140oC
+85oC
Unit
V
V
V
MHz
MHz
MHz
oC
oC
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
DSP Instruction Rate, Core Clock
Peripheral Clock Rate
Input Clock Frequency
Silicon Junction Temperature
Ambient Operating Temperature
–40oC
1
The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be
disabled.
2
The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK 2, up to a maximum of a 75 MHz HCLK for the
ADSP-21990BBC.
3
In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock
generation PLL circuit and the associated frequency ratio.
4
The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to
ensure that the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not
exceeded.
RECOMMENDED OPERATING CONDITIONS—ADSP-21990BST
Parameter
Min
Typ
Max
Unit
V
DDINT
V
DDEXT
AVDD
CCLK
HCLK
1, 2
CLKIN
3
T
JUNC
4
T
AMB
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
DSP Instruction Rate, Core Clock
Peripheral Clock Rate
Input Clock Frequency
Silicon Junction Temperature
Ambient Operating Temperature
2.375
3.135
2.375
0
0
0
2.5
3.3
2.5
2.625
3.465
2.625
160
80
160
+140oC
+85oC
V
V
V
MHz
MHz
MHz
oC
oC
–40oC
1
The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be
disabled.
2
The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK 2, up to a maximum of an 80 MHz HCLK for the
ADSP-21990BST.
3
In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock
generation PLL circuit and the associated frequency ratio.
4
The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to
ensure that the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not
exceeded.
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