參數(shù)資料
型號(hào)： ADSP-2196MKCA-160X
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 16-BIT, 160 MHz, OTHER DSP, PBGA144
封裝： MINI, BGA-144
文件頁(yè)數(shù)： 28/68頁(yè)
文件大?。?/td> 897K
代理商： ADSP-2196MKCA-160X
For current information contact Analog Devices at 800/262-5643
ADSP-2196
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
28
REV. PrA
External Port Write Cycle Timing
Table 11
and
Figure 14
describe external port write operations.
The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates
and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP
to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see
the External Port chapter in the
ADSP-219x/2191 DSP Hardware Reference
Table 11. External Port Write Cycle Timing
Parameter
Description
1, 2, 3
1
t
HCLK
is the peripheral clock period.
2
These are preliminary timing parameters that are based on worst-case operating conditions.
3
The pad loads for these timing parameters are 20 pF.
4
EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds
to HCLK (at similar clock ratios).
Min
Max
Unit
Switching Characteristics
t
CWA
EMI
4
clock low to WR asserted delay
2.8
ns
t
CSWS
Chip select asserted to WR de-asserted delay
4.3
6.5
ns
t
AWS
Address valid to WR setup and delay
4.9
7.0
ns
t
AKS
ACK asserted to EMI clock high delay
6.0
ns
t
WSCS
WR de-asserted to chip select de-asserted
4.8
7.0
ns
t
WSA
WR de-asserted to address invalid
4.5
6.6
ns
t
CWD
EMI clock low to WR de-asserted delay
2.5
2.7
ns
t
WW
WR strobe pulsewidth
t
HCLK
–0.5
ns
t
CDA
WR to data enable access delay
1.5
4.1
ns
t
CDD
WR to data disable access delay
3.3
7.4
ns
t
DSW
Data valid to WR de-asserted setup
t
HCLK
–1.4
t
HCLK
+4.8
ns
t
DHW
WR de-asserted to data invalid hold time; wt_hold=0
3.4
7.4
ns
t
DHW
WR de-asserted to data invalid hold time; wt_hold=1
t
HCLK
+3.4
t
HCLK
+7.4
ns
Timing Requirement
t
AKW
ACK strobe pulsewidth
10.0
ns
相關(guān)PDF資料
PDF描述
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