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| 型號： | ADSP-2195 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LM2991 Negative Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Qty per Container: 25; Container: Rail |
| 中文描述： | DSP的微機(jī) |
| 文件頁數(shù)： | 10/68頁 |
| 文件大?。?/td> | 951K |
| 代理商： | ADSP-2195 |
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For current information contact Analog Devices at 800/262-5643
ADSP-2195
set of parameters—called a DMA descriptor. When succes-
sive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one
DMA sequence auto-initiates and starts the next sequence.
DMA sequences do not contend for bus access with the DSP
core, instead DMAs “steal” cycles to access memory.
All DMA transfers use the DMA bus shown in the func-
tional block diagram
on page 1
. Because all of the
peripherals use the same bus, arbitration for DMA bus
access is needed. The arbitration for DMA bus access
appears in
Table 4
.
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
10
REV. PrA
Host Port
The ADSP-2195’s Host port functions as a slave on the
external bus of an external Host. The Host port interface
lets a Host read from or write to the DSP’s memory space,
boot space, or internal I/O space. Examples of Hosts include
external microcontrollers, microprocessors, or ASICs.
The Host port is a multiplexed address and data bus that
provides both an 8-bit and a 16-bit data path and operates
using an asynchronous transmission protocol. Through this
port, an off-chip Host can directly access the DSP’s entire
memory space map, boot memory space, and internal I/O
space. To access the DSP’s internal memory space, a Host
steals one cycle per access from the DSP. A Host access to
the DSP’s external memory uses the external port interface
and does not stall (or steal cycles from) the DSP’s core.
Because a Host can access internal I/O memory space, a
Host can control any of the DSP’s I/O mapped peripherals.
The Host port is most efficient when using the DSP as a
slave and uses DMA to automate the incrementing of
addresses for these accesses. In this case, an address does
not have to be transferred from the Host for every
data transfer.
Host Port Acknowledge (HACK) Modes
The Host port supports a number of modes (or protocols)
for generating a HACK output for the host. The host selects
ACK or Ready Modes using the HACK_P and HACK pins.
The Host port also supports two modes for address control:
Address Latch Enable (ALE) and Address Cycle Control
(ACC) modes. The DSP auto-detects ALE versus ACC
Mode from the HALE and HWR inputs.
The host port HACK signal polarity is selected (only at
reset) as active high or active low, depending on the value
driven on the HACK_P pin.The HACK polarity is stored
into the host port configuration register as a read only bit.
The DSP uses HACK to indicate to the Host when to
complete an access. For a read transaction, a Host can
proceed and complete an access when valid data is present
in the read buffer and the host port is not busy doing a write.
For a write transactions, a Host can complete an access
when the write buffer is not full and the host port is not busy
doing a write.
Two mode bits in the Host Port configuration register
HPCR [7:6] define the functionality of the HACK line.
HPCR6 is initialized at reset based on the values driven on
HACK and HACK_P pins (shown in
Table 5
); HPCR7 is
always cleared (0) at reset. HPCR [7:6] can be modified
after reset by a write access to the host port
configuration register.
Table 4. I/O Bus Arbitration Priority
DMA Bus Master
Arbitration Priority
SPORT0 Receive DMA
0—Highest
SPORT1 Receive DMA
1
SPORT2 Receive DMA
2
SPORT0 Transmit DMA
3
SPORT1 Transmit DMA
4
SPORT2 Transmit DMA
5
SPI0 Receive/Transmit DMA
6
SPI1 Receive/Transmit DMA
7
UART Receive DMA
8
UART Transmit DMA
9
Host Port DMA
10
Memory DMA
11—Lowest
Table 5. Host Port Acknowledge Mode Selection
Values Driven At
Reset
HPCR [7:6]
Initial Values
Acknowledge
Mode
HACK_P
HACK
Bit 7
Bit 6
0
0
0
1
Ready Mode
0
1
0
0
ACK Mode
1
0
0
0
ACK Mode
1
1
0
1
Ready Mode
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