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參數(shù)資料
| 型號(hào)： | ADSP-2189 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 244K |
| 代理商： | ADSP-2189 |
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REV. A
ADSP-2189M
–
11
–
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written while the ADSP-2189M
is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (
IS
) latches
this value into the IDMAA register.
Once the address is stored, data can then be either read from, or
written to, the ADSP-2189M’s on-chip memory. Asserting the
select line (
IS
) and the appropriate read or write line (
IRD
and
IWR
respectively) signals the ADSP-2189M that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (
IS
) and address latch enable (IAL) di-
rects the ADSP-2189M to write the address onto the IAD0-14
bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA
latches the address. If Bit 15 is set to 1, IDMA latches into the
OVLAY register. This register, shown below, is memory
mapped at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host.
Refer to the following figures for more information on IDMA
and DMA memory maps.
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10
9
8
DM(0 3FE0)
IDMAA ADDRESS
IDMAD DESTINATION MEMORY TYPE:
0 = PM
1 = DM
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
7
6
5
4
3
2
1
0
IDMA OVERLAY
9
8
DM(0 3FE7)
RESERVED SET TO 0
ID DMOVLAY
ID PMOVLAY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15 14 13 12 11 10
7
6
5
4
3
2
1
0
Figure 10. IDMA Control/OVLAY Registers
ACCESSIBLE WHEN
ALWAYS
ACCESSIBLE
AT ADDRESS
0 0000
–
0 1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
ACCESSIBLE WHEN
0 2000
–
0 3FFF
0 2000
–
0 3FFF
0 2000
–
0 3FFF
PROGRDMA
OVLAY
NOTE: IDMA AND BDMA HAVEN SEPARATE
DMA
DATA MEMORY
OVLAY
ACCESSIBLE WHEN
DMOVLAY = 7
ACCESSIBLE WHEN
DMOVLAY = 6
0 0000
–
0 1FFF
0 0000
–
0 1FFF
ACCESSIBLE WHEN
ALWAYS
ACCESSIBLE
AT ADDRESS
0 2000
–
0 3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
ACCESSIBLE WHEN
0 0000
–
0 1FFF
0 0000
–
0 1FFF
0 0000
–
0 1FFF
Figure 11. Direct Memory Access
—
PM and DM Memory
Maps
Bootstrap Loading (Booting)
The ADSP-2189M has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits.
When the MODE pins specify BDMA booting, the ADSP-2189M
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
ADSP-2189M. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
The ADSP-2189M can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2189M boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADSP-2189M | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
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