參數(shù)資料
型號(hào)： ADSP-2186NKCA-320
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 40 MHz, OTHER DSP, PBGA144
封裝： MO-205AC, BGA-144
文件頁(yè)數(shù)： 37/48頁(yè)
文件大?。?/td> 1571K
代理商： ADSP-2186NKCA-320
–37–
REV. 0
ADSP-218xN Series
IDMA Read, Short Read Cycle
Table 25. IDMA Read, Short Read Cycle
Parameter
1, 2
Timing Requirements:
t
IKR
t
IRP1
t
IRP2
Switching Characteristics:
t
IKHR
t
IKDH
t
IKDD
t
IRDE
t
IRDV
Min
Max
Unit
IACK Low before Start of Read
3
Duration of Read (DM/PM1)
4
Duration of Read (PM2)
5
0
10
10
ns
ns
ns
2t
CK
– 5
t
CK
– 5
IACK High after Start of Read
3
IAD15–0 Data Hold after End of Read
6
IAD15–0 Data Disabled after End of Read
6
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
10
ns
ns
ns
ns
ns
0
10
0
10
1
Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) bit 14 of the IDMA overlay
register, and is disabled by default upon reset.
2
Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3
Start of Read = IS Low and IRD Low.
4
DM Read or first half of PM Read.
5
Second half of PM Read.
6
End of Read = IS High or IRD High.
Figure 34. IDMA Read, Short Read Cycle
t
IRP
t
IKR
PREVIOUS
DATA
t
IKHR
t
iRDV
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD
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