參數(shù)資料
型號(hào)： ADSP-2185LKST-115
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 26.3 MHz, OTHER DSP, PQFP100
封裝： MS-026BED, LQFP-100
文件頁(yè)數(shù)： 27/31頁(yè)
文件大?。?/td> 223K
代理商： ADSP-2185LKST-115
ADSP-2185L
–27–
REV. A
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements
:
t
IKR
t
IRK
IACK
Low before Start of Read
1
End of Read after
IACK
Low
2
0
2
ns
ns
Switching Characteristics
:
t
IKHR
t
IKDS
t
IKDH
t
IKDD
t
IRDE
t
IRDV
t
IRDH1
t
IRDH2
IACK
High after Start of Read
1
IAD15–0 Data Setup before
IACK
Low
IAD15–0 Data Hold after End of Read
2
IAD15–0 Data Disabled after End of Read
2
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)
3
IAD15–0 Previous Data Hold after Start of Read (PM2)
4
4
0.5t
CK
– 7
0
15
ns
ns
ns
ns
ns
ns
ns
ns
10
0
15
2t
CK
– 5
t
CK
– 5
NOTES
1
Start of Read =
IS
Low and
IRD
Low.
2
End of Read =
IS
High or
IRD
High.
3
DM read or first half of PM read.
4
Second half of PM read.
t
IRK
t
IKR
PREVIOUS
DATA
READ
DATA
t
IKHR
t
IKDS
t
IRDV
t
IRDH
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD
Figure 28. IDMA Read, Long Read Cycle
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