參數(shù)資料
型號(hào)： ADSP-2185
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁(yè)數(shù)： 9/31頁(yè)
文件大?。?/td> 223K
代理商： ADSP-2185
ADSP-2185L
–9–
REV. A
DATA MEMORY
Data Memory (Full Memory Mode)
is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2185L has 16K words on Data
Memory RAM on chip, consisting of 16,352 user-accessible lo-
cations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus. All internal accesses complete in one cycle.
Accesses to external memory are timed using the wait states
specified by the DWAIT register.
ACCESSIBLE WHEN
ACCESSIBLE WHEN
3MAPPED
REGISTERS
0
x
3FFF
0
x
2000
0
x
1FFF
IN8160
WORDS
0
x
0000
DATA MEMORY
ADDRESS
AALWAYS
0
x
2000 – 0
x
3FFF
ACDMOVLAY = 0
INTERNAL
EXTERNAL
0
x
0000–
0
x
1FFF
0
x
0000–
0
x
1FFF
0
x
0000–
0
x
1FFF
DATA MEMORY
8K INOR
EXTERNAL 8K
0
x
3FE0
0
x
3FDF
Figure 5. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table IV.
Table IV. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
0
1
Internal
External
Overlay 1
Not Applicable
0
Not Applicable
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
1
I/O Space (Full Memory Mode)
The ADSP-2185L supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are un-
defined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table V.
Table V. Wait States
Address Range
Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
Composite Memory Select (
CMS
)
The ADSP-2185L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The
CMS
signal is generated
to have the same timing as each of the individual memory select
signals (
PMS
,
DMS
,
BMS
,
IOMS
) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the
CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the
PMS
and
DMS
bits in the
CMSSEL register and use the
CMS
pin to drive the chip select
of the memory; use either
DMS
or
PMS
as the additional
address bit.
The
CMS
pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the
CMS
signal at the same time as the
selected memory select signal. All enable bits default to 1 at re-
set, except the
BMS
bit.
Boot Memory Select (
BMS
) Disable
The ADSP-2185L also lets you boot the processor from one ex-
ternal memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the
CMS
to select the first external memory space for
BDMA transfers and
BMS
to select the second external memory
space for booting. The
BMS
signal can be disabled by setting
Bit 3 of the System Control Register to 1. The System Control
Register is illustrated in Figure 6.
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
15 14
13 12 11
10
9
8
7
6
5
4
3
2
1
0
DM (0
3
3FFF)
SYSTEM CONTROL REGISTER
1 = ENABLSPORT0 ENABLE
SPORT1 ENABLE
1 = ENABLED, 0 = DISABLED
SP1 = SERIAL PORT
0 = FI, FO,
IRQ0
,
IRQ1
, SCLK
PWAIT
BMS
ENABLE
0 = ENABLED, 1 = DISABLED
Figure 6. System Control Register
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 7. The byte memory space consists of 256 pages,
each of which is 16K
×
8.
BDMA CONTROL
9
8
BMPAGE
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
15 14 13 12 11 10
7
6
5
4
3
2
1
0
DM (0
3
3FE3)
Figure 7. BDMA Control Register
The byte memory space on the ADSP-2185L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg
×
8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
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