參數(shù)資料
型號: ADSP-2184N
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: DSP微機(jī)
文件頁數(shù): 38/48頁
文件大?。?/td> 1571K
代理商: ADSP-2184N
ADSP-218xN Series
–38–
REV. 0
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter
1
Timing Requirements:
t
IKR
t
IRP
Switching Characteristics:
t
IKHR
t
IKDH
t
IKDD
t
IRDE
t
IRDV
Min
Max
Unit
IACK Low before Start of Read
2
Duration of Read
3
0
10
ns
ns
IACK High after Start of Read
2
IAD15–0 Previous Data Hold after End of Read
3
IAD15–0 Previous Data Disabled after End of Read
3
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
10
ns
ns
ns
ns
ns
0
10
0
10
1
Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing
to the register or by an external host writing to the register. Disabled by default.
2
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3
End of Read = IS High or IRD High.
Figure 35. IDMA Read, Short Read Cycle in Short Read Only Mode
t
IRP
t
IKR
PREVIOUS
DATA
t
IKHR
t
IRDV
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD
LEGEND:
IMPLIES THAT
IS
AND
IRD
CAN BE
HELD INDEFINITELY BY HOST
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