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參數(shù)資料
| 型號(hào)： | ADSP-2183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LM2941/LM2941C 1A Low Dropout Adjustable Regulator; ; Container: Tray |
| 中文描述： | DSP的微機(jī) |
| 文件頁(yè)數(shù)： | 14/31頁(yè) |
| 文件大小： | 252K |
| 代理商： | ADSP-2183 |
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ADSP-2183
–14–
REV. C
Parameter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements
:
t
CKI
t
CKIL
t
CKIH
Switching Characteristics
:
t
CKL
t
CKH
t
CKOH
CLKIN Period
CLKIN Width Low
CLKIN Width High
38
15
15
100
ns
ns
ns
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5t
CK
– 7
0.5t
CK
– 7
0
ns
ns
ns
20
Control Signals
Timing Requirement
:
t
RSP
RESET
Width Low
5t
CK1
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKIL
t
CKOH
t
CKH
t
CKL
t
CKIH
t
CKI
Figure 8. Clock Signals
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements
:
t
IFS
t
IFH
Switching Characteristics
:
t
FOH
t
FOD
IRQx
, FI, or PFx Setup before CLKOUT Low
1, 2, 3, 4
IRQx
, FI, or PFx Hold after CLKOUT High
1, 2, 3, 4
0.25t
CK
+ 15
0.25t
CK
ns
ns
Flag Output Hold after CLKOUT Low
5
Flag Output Delay from CLKOUT Low
5
0.5t
CK
– 7
ns
ns
0.5t
CK
+ 6
NOTES
1
If
IRQx
and FI inputs meet t
and t
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx
=
IRQ0
,
IRQ1
,
IRQ2
,
IRQL0
,
IRQL1
,
IRQE
.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
t
FOD
t
FOH
t
IFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx
t
IFH
Figure 9. Interrupts and Flags
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