參數(shù)資料
型號(hào)： ADSP-2181KST-115
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 14.4 MHz, OTHER DSP, PQFP128
封裝： METRIC, PLASTIC, TQFP-128
文件頁(yè)數(shù)： 4/32頁(yè)
文件大?。?/td> 290K
代理商： ADSP-2181KST-115
REV. D
ADSP-2181
–4–
SPORT s support serial data word lengths from 3 to 16 bits
and provide optional A-law and
μ
-law companding according
to CCIT T recommendation G.711.
SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
SPORT s can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
SPORT 0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
SPORT 1 can be configured to have two external interrupts
(
IRQ0
and
IRQ1
) and the Flag In and Flag Out signals. T he
internally generated serial clock may still be used in this
configuration.
Pin Descriptions
T he ADSP-2181 is available in 128-lead T QFP and 128-lead
PQFP packages.
PIN FUNCT ION DE SCRIPT IONS
#
of
Input/
Pins
Output
Function
14
O
Address Output Pins for Program,
Data, Byte, and I/ O Spaces
24
I/O
Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)
1
I
Processor Reset Input
1
I
Edge- or Level-Sensitive
Interrupt Request
Pin
Name(s)
Address
Data
RESET
IRQ2
IRQL0
,
IRQL1
2
I
Level-Sensitive Interrupt
Requests
Edge-Sensitive Interrupt
Request
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Program Memory Select Output
Data Memory Select Output
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Memory Map Select Input
Boot Option Control Input
IRQE
1
I
BR
BG
BGH
PMS
DMS
BMS
IOMS
CMS
RD
WR
MMAP
BMODE
CLK IN,
X T AL
1
1
1
1
1
1
1
1
1
1
1
1
I
O
O
O
O
O
O
O
O
O
I
I
2
I
Clock or Quartz Crystal Input
#
of
Pins
Pin
Name(s)
Input/
Output
Function
CLK OUT
SPORT 0
SPORT 1
1
5
5
O
I/O
I/O
Processor Clock Output
Serial Port I/O Pins
Serial Port 1
or
T wo External
IRQ
s, Flag In and Flag Out
IDMA Port Read/Write Inputs
IDMA Port Select
IDMA Port Address Latch
Enable
IDMA Port Address/Data Bus
IDMA Port Access Ready
Acknowledge
Power-Down Control
Power-Down Control
IRD
,
IWR
IS
IAL
2
1
1
I
I
I
IAD
IACK
16
1
I/O
O
PWD
PWDACK
FL0, FL1,
FL2
PF7:0
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
GND
VDD
1
1
I
O
3
8
1
1
1
1
1
1
1
1
1
11
6
O
I/O
*
*
*
*
*
*
*
*
*
–
–
Output Flags
Programmable I/O Pins
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
Ground Pins
Power Supply Pins
*T hese ADSP-2181 pins must be connected
only
to the EZ-ICE
connector in
the target system. T hese pins have no function except during emulation, and
do not require pull-up or pull-down resistors.
Interrupts
T he interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
T he ADSP-2181 provides four dedicated external interrupt
input pins,
IRQ2
,
IRQL0
,
IRQL1
and
IRQE
. In addition,
SPORT 1 may be reconfigured for
IRQ0
,
IRQ1
, FLAG_IN and
FLAG_OUT , for a total of six external interrupts. T he ADSP-
2181 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. T he interrupt levels are internally prioritized and
individually maskable (except power down and reset). T he
IRQ2
,
IRQ0
and
IRQ1
input pins can be programmed to be
either level- or edge-sensitive.
IRQL0
and
IRQL1
are level-
sensitive and
IRQE
is edge sensitive. T he priorities and vector
addresses of all interrupts are shown in T able I.
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