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參數(shù)資料
| 型號(hào)： | ADSP-2181BS-133 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 16.67 MHz, OTHER DSP, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 290K |
| 代理商： | ADSP-2181BS-133 |
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ADSP-2181
–5–
REV. D
T able I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Address (Hex)
Source of Interrupt
Reset (or Power-Up with PUCR = 1) 0000
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT 0 T ransmit
SPORT 0 Receive
IRQE
BDMA Interrupt
SPORT 1 T ransmit or
IRQ1
SPORT 1 Receive or
IRQ0
T imer
(
Highest Priority
)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
(
Lowest Priority
)
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK ; the highest priority unmasked interrupt is then
selected. T he power-down interrupt is nonmaskable.
T he ADSP-2181 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. T his does not affect serial port autobuffering
or DMA transfers.
T he interrupt control register, ICNT L, controls interrupt nest-
ing and defines the
IRQ0
,
IRQ1
and
IRQ2
external interrupts to
be either edge- or level-sensitive. T he
IRQE
pin is an external
edge-sensitive interrupt and can be forced and cleared. T he
IRQL0
and
IRQL1
pins are external level-sensitive interrupts.
T he IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. T he stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
T he following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK . Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWE R OPE RAT ION
T he ADSP-2181 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. T hese modes are:
Power-Down
Idle
Slow Idle
T he CLK OUT pin may also be disabled to reduce external
power dissipation.
Power-Down
T he ADSP-2181 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. For detailed information about the power-
down feature, refer to the
ADSP-2100 Family User’s Manual
,
Third Edition,
“System Interface” chapter.
Quick recovery from power-down. T he processor begins
executing instructions in as few as 100 CLK IN cycles.
Support for an externally generated T T L or CMOS
processor clock. T he external clock can continue running
during power-down without affecting the lowest power
rating and 100 CLK IN cycle recovery.
Support for crystal operation includes disabling the oscil-
lator to save power (the processor automatically waits 4096
CLK IN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 100 CLK IN
cycle start up.
Power-down is initiated by either the power-down pin
(
PWD
) or the software power-down force bit.
Interrupt support allows an unlimited number of instruc-
tions to be executed before optionally powering down.
T he power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.
Context clear/save control allows the processor to con-
tinue where it left off or start with a clean context when
leaving the power-down state.
T he
RESET
pin also can be used to terminate power-
down.
Power-down acknowledge pin indicates when the proces-
sor has entered power-down.
Idle
When the ADSP-2181 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE
instruction.
Slow Idle
T he
IDLE
instruction is enhanced on the ADSP-2181 to let
the processor’s internal clock signal be slowed, further
reducing power consumption. T he reduced clock fre-
quency, a programmable fraction of the normal clock rate,
is specified by a selectable divisor given in the
IDLE
in-
struction. T he format of the instruction is
IDLE (n);
where
n
= 16, 32, 64 or 128. T his instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK , CLK OUT and timer clock,
are reduced by the same ratio. T he default form of the
instruction, when no clock divisor is given, is the standard
IDLE
instruction.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-2181KS-115 | DSP Microcomputer |
| ADSP-2181KS-133 | DSP Microcomputer |
| ADSP-2181KS-160 | DSP Microcomputer |
| ADSP-2181KST-115 | DSP Microcomputer |
| ADSP-2181KST-133 | DSP Microcomputer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2181BS-160 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| ADSP2181BST115 | 制造商:AD 功能描述:2181 ANALOG |
| ADSP-2181BST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:DSP W/LARGE RAM, 28.8MIPS I GRDE, TQFP - Bulk |
| ADSP-2181BST-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:DSP W/LARGE RAM, 33MIPS I GRDE, TQFP - Bulk 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP |
| ADSP-2181BST-160 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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