參數(shù)資料
型號(hào)： ADSP-21479KSWZ-2A
廠商： Analog Devices Inc
文件頁數(shù)： 58/72頁
文件大?。?/td> 0K
描述： IC DSP SHARC 266MHZ LP 100LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（4Mb）
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-LQFP-EP（14x14）
包裝： 托盤
其它名稱： Q6418433
Rev. A
|
Page 61 of 72
|
September 2011
OUTPUT DRIVE CURRENTS
Table 55 shows the driver types and the pins associated with
each driver. Figure 47 shows typical I-V characteristics for each
driver. The curves represent the current drive capability of the
output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 48.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 49. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 48). Figure 52 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 50, Figure 51, and Figure 52 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
Table 55. Driver Types
Driver Type
Associated Pins
A
FLAG[0–3], AMI_ADDR[23–0], DATA[15–0],
AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,
SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU,
TDO, RESETOUT, DPI[1–14], DAI[1–20],
WDTRSTO, MLBDAT, MLBSIG, MLBSO, MLBDO,
MLBCLK, SR_CLR, SR_LAT, SR_LDO[17–0],
SR_SCLK, SR_SDI
BSDCLK, RTCLKOUT
Figure 47. Typical Drive at Junction Temperature
Figure 49. Voltage Reference Levels for AC Measurements
SWEEP (V
DDEXT) VOLTAGE (V)
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
0
100
200
SOURCE/SINK
(V
DDEXT
)CURRENT
(mA)
150
50
-100
-200
-150
-50
V
OH 3.13 V, 125 °C
V
OL 3.13 V, 125 °C
TYPE A
TYPE B
INPUT
OR
OUTPUT
1.5V
Figure 48. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 50. Typical Output Rise/Fall Time (20% to 80%,
VDD_EXT = Max)
T1
ZO = 50
: (impedance)
TD = 4.04
r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
:
0.5pF
70
:
400
:
45
:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
:
LOAD CAPACITANCE (pF)
6
0
7
4
2
1
3
RISE
AND
FALL
TIMES
(ns)
125
200
100
25
175
50
75
150
5
y = 0.0331x + 0.2662
y = 0.0184x + 0.3065
y = 0.0421x + 0.2418
y = 0.0206x + 0.2271
TYPE A DRIVE FALL
TYPE A DRIVE RISE
TYPE B DRIVE FALL
TYPE B DRIVE RISE
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參數(shù)描述
ADSP-21479SBC2-EP 功能描述:IC DSP SHARC 266MHZ LP 制造商:analog devices inc. 系列:SHARC? 包裝:托盤 零件狀態(tài):在售 類型:浮點(diǎn) 接口:DAI，DPI，EBI/EMI，I2C，SPI，SPORT，UART/USART 時(shí)鐘速率:266MHz 非易失性存儲(chǔ)器:ROM（4Mb） 片載 RAM:5Mb 電壓 - I/O:3.30V 電壓 - 內(nèi)核:1.20V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1
ADSP-21483KSWZ-2B 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21483KSWZ-3AB 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21483KSWZ-3B 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21483KSWZ-4B 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
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