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參數(shù)資料
型號: ADSP-21478KBCZ-2A
廠商: Analog Devices Inc
文件頁數(shù): 23/76頁
文件大小: 0K
描述: IC DSP SHARK 266MHZ 196CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI,EBI/EMI,I²C,SPI,SPORT,UART/USART
時鐘速率: 266MHz
非易失內(nèi)存: ROM(4Mb)
芯片上RAM: 3Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 196-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 196-CSPBGA(12x12)
包裝: 托盤
Rev. C
|
Page 3 of 76
|
July 2013
GENERAL DESCRIPTION
The ADSP-2147x SHARC
processors are members of the
SIMD SHARC family of DSPs that feature Analog Devices’
Super Harvard Architecture. The processors are source code
compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,
ADSP-2146x, and ADSP-2116x DSPs as well as with first
generation ADSP-2106x SHARC processors in SISD (single-
instruction, single-data) mode. These processors are 32-bit/
40-bit floating-point processors optimized for high perfor-
mance audio applications with a large on-chip SRAM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
digital applications interface (DAI).
Table 1 shows performance benchmarks for the ADSP-2147x
processors. Table 2 shows the features of the individual product
offerings.
The diagram on Page 1 shows the two clock domains (core and
I/O processor) that make up the ADSP-2147x processors. The
core clock domain contains the following features.
Two processing elements (PEx, PEy), each of which com-
prises an ALU, multiplier, shifter, and data register file
Two data address generators (DAG1, DAG2)
A program sequencer with instruction cache
PM and DM buses capable of supporting 2 × 64-bit data
transfers between memory and the core at every core pro-
cessor cycle
One periodic interval timer with pinout
On-chip SRAM (up to 5M bit)
A JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points, which allows flexible exception handling.
Table 1. Processor Benchmarks
Benchmark Algorithm
Speed
(at 300 MHz)
Speed
(at 200 MHz)
1024 Point Complex FFT
(Radix 4, with Reversal)
30.59 μs
45.885 μs
FIR Filter (per Tap)
1
1 Assumes two files in multichannel SIMD mode.
1.66 ns
2.49 ns
IIR Filter (per Biquad)
1
6.65 ns
9.975 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
14.99 ns
26.66 ns
22.485 ns
39.99 ns
Divide (y/×)
11.61 ns
17.41 ns
Inverse Square Root
18.08 ns
27.12 ns
Table 2. ADSP-2147x Family Features
Feature
ADSP
-2147
7
ADSP
-2147
8
ADSP
-2147
9
Frequency
200 MHz
Up to 300 MHz
RAM
2M bits
3M bits
5M bits
ROM
N/A
4M bits
Pulse-Width Modulation
3
4 units (3 in 100-lead
package)
External Port Interface
(SDRAM, AMI)
1
No
Yes, 16-Bit
Serial Ports
8
Direct DMA from SPORTs
to External Memory
No
Yes
FIR, IIR, FFT Accelerator
Yes
MediaLB Interface
No
Automotive models
only
Watch Dog Timer2
No
Yes
Real-Time Clock
No
Yes
Shift Register
No
Yes
IDP/PDAP
Yes
UART
1
DAI (SRU)/DPI (SRU2)
20/14 Pins
S/PDIF Transceiver
1
SPI
2
TWI
1
SRC SNR Performance
–128 dB
Thermal Diode
4
Yes
VISA Support
Yes
Package1
100-Lead
LQFP
88-Lead
LFCSP_VQ
196-Ball CSP_BGA
100-Lead LQFP
88-lead LFCSP_VQ
1 The 100-lead and 88-lead packages of the processors do not contain an external
port. The SDRAM controller pins must be disabled when using this package.
For more information, see Pin Function Descriptions on Page 17.
2 Available on the 196-ball CSP_BGA package only.
3 Real Time Clock (RTC) is supported only for products with a temperature range
of 0°C to +70°C and not supported for all other temperature grades.
4 Available on the 88-lead and 100-lead packages only.
Table 2. ADSP-2147x Family Features (Continued)
Feature
ADSP
-21477
ADSP
-21478
ADSP
-21479
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