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參數(shù)資料
| 型號： | ADS802E |
| 英文描述： | 12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位，10MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 283K |
| 代理商： | ADS802E |
11
ADS802
vides good high frequency AC performance. It is important
to select a transformer that gives low distortion and does not
exhibit core saturation at full scale voltage levels. Since the
transformer does not appreciably load the ladder, there is no
need to buffer the common-mode (CM) output in this in-
stance. In general, it is advisable to keep the current draw
from the CM output pin below 0.5
μ
A to avoid nonlinearity
in the internal reference ladder. A FET input operational
amplifier such as the OPA130 can provide a buffered refer-
ence for driving external circuitry. The analog IN and IN
inputs should be bypassed with 22pF capacitors to minimize
track/hold glitches and to improve high input frequency
performance.
Figure 5 illustrates another possible low cost interface circuit
which utilizes resistors and capacitors in place of a trans-
former. Depending on the signal bandwidth, the component
values should be carefully selected in order to maintain the
performance outlined in the data sheet. The input capacitors,
C
IN
, and the input resistors, R
IN
, create a high-pass filter with
the lower corner frequency at f
C
= 1/(2
π
R
IN
C
IN
). The corner
frequency can be reduced by either increasing the value of
R
IN
or C
IN
. If the circuit operates with a 50
or 75
impedance level, the resistors are fixed and only the value of
the capacitor can be increased. Usually AC-coupling capaci-
tors are electrolytic or tantalum capacitors with values of
1
μ
F or higher. It should be noted that these large capacitors
become inductive with increased input frequency, which
could lead to signal amplitude errors or oscillation. To
maintain a low AC-coupling impedance throughout the sig-
nal band, a small value (e.g. 1
μ
F) ceramic capacitor could be
added in parallel with the polarized capacitor.
Capacitors C
SH1
and C
SH2
are used to minimize current
glitches resulting from the switching in the input track and
hold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors R
SER1
and R
SER2
were added in series with
each input. The cut-off frequency of the filter is determined
by f
C
= 1/(2
π
R
SER
(C
SH
+C
ADC
)) where R
SER
is the resistor in
series with the input, C
SH
is the external capacitor from the
input to ground, and C
ADC
is the internal input capacitance of
the A/D converter (typically 4pF).
Resistors R
1
and R
2
are used to derive the necessary common
mode voltage from the buffered top and bottom references.
The total load of the resistor string should be selected so that
the current does not exceed 1mA. Although the circuit in
Figure 5 uses two resistors of equal value so that the common
mode voltage is centered between the top and bottom refer-
ence (+2.25V), it is not necessary to do so. In all cases the
center point, V
CM
, should be bypassed to ground in order to
provide a low impedance AC ground.
If the signal needs to be DC coupled to the input of the
ADS802, an operational amplifier input circuit is required.
In the differential input mode, any single-ended signal must
be modified to create a differential signal. This can be
accomplished by using two operational amplifiers, one in
the noninverting mode for the input and the other amplifier
in the inverting mode for the complementary input. The low
distortion circuit in Figure 6 will provide the necessary input
shifting required for signals centered around ground. It also
employs a diode for output level shifting to guarantee a low
distortion +3.25V output swing. Other amplifiers can be
used in place of the OPA642s if the lowest distortion is not
necessary. If output level shifting circuits are not used, care
must be taken to select operational amplifiers that give the
necessary performance when swinging to +3.25V with a
±
5V supply operational amplifier.
The ADS802 can also be configured with a single-ended
input full scale range of +0.25V to +4.25V by tying the
complementary input to the common-mode reference voltage
as shown in Figure 7. This configuration will result in
increased even-order harmonics, especially at higher input
frequencies. However, this tradeoff may be quite acceptable
for time-domain applications. The driving amplifier must
give adequate performance with a +0.25V to +4.25V output
swing in this case.
FIGURE 5. AC-Coupled Differential Input Circuit.
ADS8xx
*R
SER1
49.9
R
3
1k
R
2
(6k
)
R
1
(6k
)
C
2
0.1
μ
F
C
22pF
C
22pF
C
3
0.1
μ
F
C
1
0.1
μ
F
C
IN
0.1
μ
F
V
CM
C
IN
0.1
μ
F
R
IN1
25
R
IN2
25
*R
SER2
49.9
+3.25V
Top Reference
+1.25V
Bottom Reference
IN
NOTE: * indicates optional component.
IN
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| ADS802U | 12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
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| ADS804 | 12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS802E/1K | 制造商:BB 制造商全稱:BB 功能描述:12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS802U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 10 MSPS SE/Diff input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS802U/1K | 制造商:BB 制造商全稱:BB 功能描述:12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS802UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 10 MSPS SE/Diff input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS803 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit, 5MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
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