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參數(shù)資料
| 型號： | ADS801E |
| 英文描述： | 12-Bit, 25MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位，25MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 279K |
| 代理商： | ADS801E |
10
ADS801
time-align it with the data created from the following quan-
tizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
gives the ADS801 excellent differential linearity and guar-
antees no missing codes at the 12-bit level.
Since there are two pipeline stages per external clock cycle,
there is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS801 can be configured in
various ways and driven with different circuits, depending
on the nature of the signal and the level of performance
desired. The ADS801 has an internal reference that sets the
full scale input range of the A/D. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full scale range of
+1.25V to +3.25V. Since each input is 2V peak-to-peak and
180
°
out of phase with the other, a 4V differential input
signal to the quantizer results. As shown in Figure 3, the
positive full scale reference (REFT) and the negative full
scale (REFB) are brought out for external bypassing. In
addition, the common-mode voltage (CM) may be used as a
reference to provide the appropriate offset for the driving
circuitry. However, care must be taken not to appreciably
load this reference node. For more information regarding
external references, single-ended input, and ADS801 drive
circuits, refer to the applications section.
APPLICATIONS
DRIVING THE ADS801
The ADS801 has a differential input with a common-mode
of +2.25V. For AC-coupled applications, the simplest way
to create this differential input is to drive the primary
winding of a transformer with a single-ended input. A
differential output is created on the secondary if the center
tap is tied to the common-mode voltage of +2.25V per
Figure 4. This transformer-coupled input arrangement pro-
+FS (IN = +3.25V, IN = +1.25V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1.25V, IN = +3.25V)
111111111111
111111111111
111111111110
111000000000
110000000000
101000000000
100000000001
100000000000
011111111111
011000000000
010000000000
001000000000
000000000001
000000000000
011111111111
011111111111
011111111110
011000000000
010000000000
001000000000
000000000001
000000000000
111111111111
111000000000
110000000000
101000000000
100000000001
100000000000
Note: In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
DIGITAL OUTPUT DATA
The 12-bit output data is provided at CMOS logic levels.
The standard output coding is Straight Offset Binary where
a full scale input signal corresponds to all “1’s” at the output.
This condition is met with pin 19 “LO” or Floating due to
an internal pull-down resistor. By applying a logic “HI”
voltage to this pin, a Binary Two’s Complement output will
be provided where the most significant bit is inverted. The
digital outputs of the ADS801 can be set to a high imped-
ance state by driving OE (pin 18) with a logic “HI”. Normal
operation is achieved with pin 18 “LO” or Floating due to
internal pull-down resistors. This function is provided for
testability purposes and is not meant to drive digital buses
directly or be dynamically changed during the conversion
process.
TABLE I. Coding Table for the ADS801.
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. The rising
and falling edges of the externally applied convert command
clock control the various interstage conversions in the pipe-
line. Therefore, the duty cycle of the clock should be held at
50% with low jitter and fast rise/fall times of 2ns or less.
This is particularly important when digitizing a high fre-
quency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten
some of the interstage settling times, thus degrading the
SNR and DNL performance.
OUTPUT CODE
SOB
PIN 19
BTC
PIN 19
HI
DIFFERENTIAL INPUT
(1)
FLOATING or LO
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
+1.25V
+3.25V
2k
2k
0.1μF
0.1μF
+2.25V
REFT
REFB
CM
ADS801
To
Internal
Comparators
21
22
23
FIGURE 3. Internal Reference Structure.
Mini-Circuits
TT1-6-KK81
or equivalent
22
26
27
CM
IN
IN
ADS801
AC Input
Signal
22pF
22pF
0.1
μ
F
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| ADS801U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 25 MSPS SE/Diff inputs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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