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參數(shù)資料
| 型號： | ADS7861EB |
| 英文描述： | CMOS 4-Bit-by-16-Word FIFO Register 16-PDIP -55 to 125 |
| 中文描述： | 雙通道，為500kHz，12位，2通道，同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 226K |
| 代理商： | ADS7861EB |
12
ADS7861
Mode II (M0 = 0, M1 = 1)
With M1 set to ‘1’, the ADS7861 will output data on the
Serial Data A pin only. All other pins function in the same
manner as Mode I except that the Serial Data B output will
tri-state (i.e., high impedance) after a conversion following
M1 going HIGH. Another difference in this mode involves
the CONVST pin. Since it takes 32 clock cycles to output
the results from both A/D converters (rather than 16 when
M1 = 0), the ADS7861 will take 4
μ
s to complete a
conversion on both A/Ds. Therefore, every second CONVST
command will be ignored by the ADS7861 since it will
require two conversion cycles to transmit both channels
out the serial A port. See Figure 11.
Mode III (M0 = 1, M1 = 0)
With M0 set to ‘1’, the ADS7861 will cycle through Chan-
nels 0 and 1 sequentially (the A0 pin is ignored). At the same
time, setting M1 to ‘0’ places both Serial Outputs, A and B,
in the active mode. See Figure 12.
Mode IV (M0 = 1, M1 = 1)
Similar to Mode II, Mode IV uses the Serial A output line to
transmit data exclusively. Following the first conversion
after M1 goes HIGH, the serial B output will go into tri-
state. See Figure 13. As in Mode II, the second CONVST
command is always ignored when M1 = 1.
READING DATA
In all four timing diagrams, the CONVST pin and the RD
pins are tied together. If so desired, the two lines can be
separated. Data on the Serial Output pins (A and B) will
become valid following the third external clock cycle fol-
lowing a RD LOW. Refer to Table II for data output format.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7861 circuitry. This is particu-
larly true if the CLOCK input is approaching the maximum
throughput rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. Their error can change if the external event
changes in time with respect to the CLOCK input.
With this in mind, power to the ADS7861 should be clean
and well bypassed. A 0.1
μ
F ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1
μ
F to 10
μ
F capacitor is recommended. If needed, an even
larger capacitor and a 5
or 10
series resistor may be used
to low pass filter a noisy supply. On average, the ADS7861
draws very little current from an external reference as the
reference voltage is internally buffered. However, glitches
from the conversion process appear at the V
REF
input and the
reference source must be able to handle this. Whether the
reference is internal or external, the V
REF
pin should be
bypassed with a 0.1
μ
F capacitor. An additional larger ca-
pacitor may also be used, if desired. If the reference voltage
is external and originates from an op amp, make sure that it
can drive the bypass capacitor or capacitors without oscilla-
tion. No bypass capacitor is necessary when using the
internal reference (tie pin 10 directly to pin 11).
The GND pin should be connected to a clean ground point.
In many cases, this will be the ‘a(chǎn)nalog’ ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If required, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
APPLICATIONS
An applications section will be added featuring the ADS7862
interfacing to popular DSP processors. The updated data
sheet will be available in the near future on the Burr-Brown
web site:
http: //www.burr-brown.com/
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7861EB | 制造商:Texas Instruments 功能描述:Analog/Digital Converter IC Number of Bi |
| ADS7861EB/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861EB/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861EBG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861EG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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