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參數(shù)資料
| 型號： | ADS7861E |
| 英文描述： | CMOS 4-Bit-by-16-Word FIFO Register 16-PDIP -55 to 125 |
| 中文描述： | 雙通道，為500kHz，12位，2通道，同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 226K |
| 代理商： | ADS7861E |
3
ADS7861
PIN
NAME
DESCRIPTION
1
DGND
Digital Ground. Connect directly to analog ground (pin 12).
2
CH B1+
Non-Inverting Input Channel B1
3
CH B1–
Inverting Input Channel B1
4
CH B0+
Non-Inverting Input Channel B0
5
CH B0–
Inverting Input Channel B0
6
CH A1+
Non-Inverting Input Channel A1
7
CH A1–
Inverting Input Channel A1
8
CH A0+
Non-Inverting Input Channel A0
9
CH A0–
Inverting Input Channel A0
10
REF
IN
REF
OUT
AGND
Reference Input
11
2.5V Reference Output
12
Analog Ground. Connect directly to digital ground (pin 1).
13
+V
A
Analog Power Supply, +5VDC. Connect directly to digital
power supply (pin 24). Decouple to analog ground with a
0.1
μ
F ceramic capacitor and a 10
μ
F tantalum capacitor.
Selects between the Serial Outputs. When M1 is LOW,
both Serial Output A and Serial Output B are selected for
data transfer. When M1 is HIGH, Serial output A is
configured for both Channel A data and Channel B data;
Serial Output B goes into tri-state (i.e., high impedance).
14
M1
15
M0
Selects between two-channel and four-channel opera-
tion. When M0 is LOW, two-channel operation is se-
lected and operates in conjunction with A0. When A0 is
HIGH, Channel A1 and Channel B1 are being con-
verted. When A0 is LOW, Channel A0 and Channel B0
are being converted. When M0 is HIGH, four-channel
operation is selected. In this mode, all four channels are
converted in sequence starting with Channels A0 and
B0, followed by Channels A1 and B1.
16
A0
A0 operates in conjunction with M0. With M0 LOW and
A0 HIGH, Channel A1 and Channel B1 are converted.
With M0 LOW and A0 LOW, Channel A0 and Channel
B0 are converted.
17
CONVST
Convert Start. When CONVST switches from LOW to
HIGH, the device switches from the sample to hold
mode, independent of the status of the external clock.
18
RD
Synchronization Pulse for the Serial Output.
19
CS
Chip Select. When LOW, the Serial Output A and Serial
Output B outputs are active; when HIGH, the serial
outputs are tri-stated.
20
CLOCK
An external CMOS-compatible clock can be applied to
the CLOCK input to synchronize the conversion process
to an external source. The CLOCK pin controls the
sampling rate by the equation: CLOCK = 16 f
SAMPLE
.
BUSY goes HIGH during a conversion and returns LOW
after the third LSB has been transmitted on either the
Serial A or Serial B output pin.
21
BUSY
22
SERIAL
DATA
B
The Serial Output data word is comprised of channel
information and 12 bits of data. In operation, data is valid
on the falling edge of DCLOCK for 16 edges after the
trailing edge of the RD.
23
SERIAL
DATA
A
The Serial Output data word is comprised of channel
information and 12 bits of data. In operation, data is valid
on the falling edge of DCLOCK for 16 edges after the
trailing edge of the RD. When M1 is HIGH, both Channel
A data and Channel B data are available.
24
+V
D
Digital Power Supply, +5VDC. Connect directly to pin
13. Must be
≤
+V
A
.
PIN CONFIGURATION
Top View
SSOP
PIN DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS
Analog Inputs to AGND, Any Channel Input ........ –0.3V to (+V
D
+ 0.3V)
REF
IN
..................................................................... –0.3V to (+V
D
+ 0.3V)
Digital Inputs to DGND.......................................... –0.3V to (+V
D
+ 0.3V)
Ground Voltage Differences: AGND, DGND ...................................
±
0.3V
+V
D
to AGND ......................... –0.3V to +6V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature ................................................... +150
°
C
Operating Temperature Range ........................................–40
°
C to +85
°
C
Storage Temperature Range .........................................–65
°
C to +150
°
C
Lead Temperature (soldering, 10s)............................................... +300
°
C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifi-
cations.
DGND
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
REF
IN
REF
OUT
AGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
+V
D
SERIAL DATA A
SERIAL DATA B
BUSY
CLOCK
CS
RD
CONVST
A0
M0
M1
+V
A
ADS7861
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7861E | 制造商:BURR-BROWN 功能描述:12BIT ADC DUAL SMD 7861 SSOP24 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi |
| ADS7861E/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861E/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861EB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861EB | 制造商:Texas Instruments 功能描述:Analog/Digital Converter IC Number of Bi |
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