參數(shù)資料
型號(hào): ADS7842E
英文描述: 12-Bit, 4-Channel Parallel Output Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 12位,4通道并行輸出采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 9/13頁(yè)
文件大?。?/td> 139K
代理商: ADS7842E
9
ADS7842
THEORY OF OPERATION
The ADS7842 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6
μ
m CMOS process.
The basic operation of the ADS7842 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+V
CC
. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7842.
ANALOG INPUTS
The ADS7842 features four, single-ended inputs. The input
current into each analog input depends on input voltage and
sampling rate. Essentially, the current into the device must
charge the internal hold capacitor during the sample period.
After this capacitance has fully charged, there is no further
input current. The source of the analog input voltage must be
able to charge the input capacitance to a 12-bit settling level
within the same period, which can be as little as 350ns in
some operating modes. While the converter is in the hold
mode, or after the sampling capacitor has been fully charged,
the input impedance of the analog input is greater than 1G
.
EXTERNAL CLOCK
The ADS7842 requires an external clock to run the conver-
sion process. This clock can vary between 200kHz (12.5kHz
throughput) and 3.2MHz (200kHz throughput). The duty
cycle of the clock is unimportant as long as the minimum
HIGH and LOW times are at least 150ns and the clock
period is at least 300ns. The minimum clock frequency is set
by the leakage on the capacitors internal to the ADS7842.
BASIC OPERATION
Figure 1 shows the simple circuit required to operate the
ADS7842 with Channel 0 selected. A conversion can be
initiated by bringing the WR pin (pin 22) LOW for a
minimum of 25ns. BUSY (pin 23) will output a LOW during
the conversion process and rises only after the conversion is
complete. The 12 bits of output data will be valid on pins
7-13 and 15-19 following the rising edge of BUSY.
FIGURE 1. Basic Operation of the ADS7842.
AIN0
AIN1
AIN2
AIN3
V
REF
AGND
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
ANA
V
DIG
A1
A0
CLK
BUSY
WR
CS
RD
DB0
DB1
DB2
DB3
DB4
3.2MHz Clock
BUSY Output
Write Input
Read Input
2.2
μ
F
+5V
0V to V
REF
ADS7842
+
0.1
μ
F
+
10
μ
F
+5V Analog Supply
+
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ADS7842EB 制造商:Texas Instruments 功能描述:IC's