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參數(shù)資料
| 型號： | ADS7835EB |
| 英文描述： | CMOS Hex Inverting Buffer/Converter 16-CDIP -55 to 125 |
| 中文描述： | 12位，高速，低功耗采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 169K |
| 代理商： | ADS7835EB |
8
ADS7835
EXTERNAL REFERENCE
The internal reference is connected to the V
REF
pin and to the
internal buffer via a 10k
series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.3V
to 2.9V, corresponding to an analog input range of 2.3V to
2.9V in both cases.
While the external reference will not source significant
current into the V
REF
pin, it does have to drive the 10k
series resistor that is terminated into the 2.5V internal
reference (the exact value of the resistor will vary up to
±
30% from part to part). In addition, the V
REF
pin should
still be bypassed to ground with at least a 0.1
μ
F ceramic
capacitor (placed as close to the ADS7835 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2
μ
F tantalum capacitor shown in Figure 1.
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. The other is to provide greater
stability over temperature. (The internal reference is typi-
cally 20ppm/
°
C which translates into a full-scale drift of
roughly one output code for every 12
°
C. This does not take
into account other sources of full-scale drift.) If greater
stability over temperature is needed, then an external refer-
ence with lower temperature drift will be required.
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7835. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter addi-
tional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
the CLK may be kept LOW or HIGH.
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design consider-
ations. Figure 3 shows that CONV has timing restraints in
relation to CLK (t
CKCH
and t
CKCS
). However, if these times
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
sion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high imped-
ance and goes LOW, the conversion has started and that
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
t
CONV
t
CKP
t
CKL
t
CKH
t
CKDH
Acquisition Time
Conversion Time
Clock Period
Clock LOW
Clock HIGH
Clock Falling to Current Data
Bit No Longer Valid
Clock Falling to Next Data Valid
CONV LOW
CONV HIGH
CONV Hold after Clock Falls
(1)
CONV Setup to Clock Falling
(1)
Clock Falling to DATA Enabled
Clock Falling to DATA
High Impedance
Clock Falling to Sample Mode
Clock Falling to Power-Down Mode
CONV Falling to Hold Mode
(Aperture Delay)
CONV Rising to Sample Mode
CONV Rising to Full Power-up
CONV Changing State to DATA
High Impedance
CONV Changing State to
Power-Down Mode
CONV Falling to Start of CLK
(for hold droop < 0.1 LSB)
350
1.625
125
50
50
5
ns
μ
s
ns
ns
ns
ns
5000
15
t
CKDS
t
CVL
t
CVH
t
CKCH
t
CKCS
t
CKDE
t
CKDD
30
50
ns
ns
ns
ns
ns
ns
ns
40
40
10
10
20
70
50
100
t
CKSP
t
CKPD
t
CVHD
5
50
5
ns
ns
ns
t
CVSP
t
CVPU
t
CVDD
5
50
70
ns
ns
ns
100
t
CVPD
50
ns
t
DRP
5
μ
s
Note: (1) This timing is not required under some situations. See text for more information.
TABLE I. Timing Specifications (T
A
= –40
°
C to +85
°
C,
C
LOAD
= 30pF).
FIGURE 2. Serial Data and Clock Timing.
DATA
CLK
t
CKH
t
CKP
t
CKDH
t
CKDS
t
CKL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7835EB/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7835EB/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7835EB/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7835EB/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7835EB250 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-Bit, High-Speed, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER |
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