參數(shù)資料
型號(hào): ADS7834P
英文描述: 12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 12位高速低功耗采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 2/13頁(yè)
文件大?。?/td> 145K
代理商: ADS7834P
2
ADS7834
SPECIFICATIONS
At T
A
= –40
°
C to +85
°
C, +V
CC
= +5V, f
SAMPLE
= 500kHz, f
CLK
= 16 f
SAMPLE
, internal reference, unless otherwise specified.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
ADS7834P, E
ADS7834PB, EB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
(1)
Absolute Input Range
+IN – (–IN)
+IN
–IN
0
V
REF
6
6
6
6
6
6
V
V
V
pF
μ
A
–0.2
–0.2
V
REF
+0.2
Capacitance
Leakage Current
25
1
6
6
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
(3)
12
6
Bits
Bits
LSB
(2)
LSB
LSB
LSB
LSB
dB
dB
μ
Vrms
LSB
12
6
±
1
±
0.8
±
2
±
12
±
2
±
0.5
±
0.5
±
1
±
7
±
1
±
1
6
±
15
±
35
±
5
±
30
±
50
25
°
C
–40
°
C to +85
°
C
DC, 0.2Vp-p
1MHz, 0.2Vp-p
Common-Mode Rejection
70
50
60
1.2
6
6
6
6
Noise
Power Supply Rejection
Worst Case
, +V
CC
= 5V
±
5%
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Aperture Delay
Aperture Jitter
Step Response
1.625
0.350
6
6
μ
s
μ
s
kHz
ns
ps
ns
500
6
5
30
350
6
6
6
DYNAMIC CHARACTERISTICS
Signal-to-Noise Ratio
Total Harmonic Distortion
(4)
Signal-to-(Noise+Distortion)
Spurious Free Dynamic Range
Usable Bandwidth
V
IN
= 5Vp-p at 10kHz
V
IN
= 5Vp-p at 10kHz
V
IN
= 5Vp-p at 10kHz
V
IN
= 5Vp-p at 10kHz
SNR > 68dB
72
–78
70
78
350
6
dB
dB
dB
dB
kHz
–72
–82
72
82
6
–75
68
72
70
75
REFERENCE OUTPUT
Voltage
Source Current
(5)
Drift
Line Regulation
I
= 0
Static Load
I
OUT
= 0
4.75V
CC
5.25V
2.475
2.50
2.525
50
2.48
6
2.52
6
V
μ
A
20
0.6
6
6
ppm/
°
C
mV
REFERENCE INPUT
Range
Resistance
(6)
2.0
2.55
6
6
6
6
V
k
to Internal Reference Voltage
10
6
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
V
IH
V
IL
V
OH
V
Data Format
CMOS
6
|I
IH
|
+5
μ
A
|I
IL
|
+5
μ
A
I
OH
= –500
μ
A
I
OL
= 500
μ
A
3.0
–0.3
3.5
V
CC
+0.3
0.8
6
6
6
6
6
6
6
6
V
V
V
V
0.4
Straight Binary
6
POWER SUPPLY REQUIREMENT
+V
Quiescent Current
Specified Performance
f
SAMPLE
= 500kHz
f
SAMPLE
= 500kHz
4.75
5.25
6
6
V
2.2
0.5
11
2.5
6
6
6
6
mA
mA
mW
mW
Power Dissipation
20
6
TEMPERATURE RANGE
Specified Performance
–40
+85
6
6
°
C
6
Specifications same as ADS7834P,E.
NOTES: (1) Ideal input span, does not include gain or offset error. (2) LSB means Least Significant Bit, with V
equal to +2.5V, one LSB is 610
μ
V. (3) Measured
relative to an ideal, full-scale input (+IN – (–IN)) of 2.499V. Thus, gain error includes the error of the internal voltage reference. (4) Calculated on the first nine
harmonics of the input frequency. (5) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal
10k
resistor. (6) Can vary
±
30%.
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