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參數(shù)資料
| 型號(hào)： | ADS7832BN |
| 英文描述： | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | Autocalibrating，4通道，12位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 299K |
| 代理商： | ADS7832BN |
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ADS7832
2
ADS7832BP/ADS7832BN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
ANALOG INPUT
Voltage Input Range
Input Capacitance
On State Bias Current
Off State Bias Current
V
A
= V
D
= V
REF+
= 3.0V
0
V
REF+
V
pF
nA
nA
nA
M
LSB
40
100
10
100
T
= +25
°
C
T
A
= –40
°
C to +85
°
C
On Resistance Multiplexer
Off Resistance Multiplexer
Channel Separation
400
10
0.5
F
IN
= 1kHz, V
REF
+ = 3.0V
REFERENCE INPUT
For Specified Performance: V
REF
+
V
A
0
V
V
V
V
μ
A
V
REF
–
For Derated Performance
(2)
: V
REF
+
(V
REF
+) – (V
REF
–)
≥
2.5V
2.5
0
V
A
0.5
200
V
REF
–
Input Reference Current
100
THROUGHPUT SPEED
Conversion Time With External Clock (Including
Multiplexer Settling Time and Acquisition Time)
CLK = 1MHz
CLK = 500kHz
T
= +25
°
C
T
A
= –40
°
C to +85
°
C
17
34
μ
s
μ
s
μ
s
μ
s
V/
μ
s
μ
s
ns
With Internal Clock Using Recommended
Clock Components
Slew Rate
Multiplexer Settling Time to 1/2 LSB
Multiplexer Access Time
30
30
2
0.5
20
SAMPLING DYNAMICS
Full Power Bandwidth
Aperture Jitter
Aperture Delay
–3dB
2
MHz
ps
μ
s
ns
SRF D2 LOW
(3)
SFR D2 HIGH
5
5
DC ACCURACY
Integral Nonlinearity, All Channels
SFR D2 LOW
±
0.75
LSB
(4)
LSB
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
Command Asynchronous to External Clock
±
0.5
±
0.6
LSB
Differential Nonlinearity
No Missing Codes
Gain Error
Gain Error Drift
Offset Error
±
0.75
LSB
Guaranteed
All Channels
±
0.5
LSB
ppm/
°
C
Between Calibration Cycles
All Channels
SFR D2 LOW
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
Command Asynchronous to External Clock
Between Calibration Cycles
SFR D2 LOW
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
Command Asynchronous to External Clock
SFR D2 LOW
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
Command Asynchronous to External Clock
V
D
= V
A
= +3.3V
±
10% (without recalibration)
±
0.2
±
0.75
LSB
LSB
±
1
±
4
LSB
Offset Error Drift
±
0.2
±
0.5
ppm/
°
C
ppm/
°
C
±
1
ppm/
°
C
Channel-to-Channel Mismatch
±
0.25
±
0.5
LSB
LSB
±
1
LSB
Power Supply Sensitivity
±
0.125
LSB
AC ACCURACY
Signal-to-(Noise + Distortion) Ratio
f
IN
= 1kHz
f
IN
= 50kHz
f
IN
= 50kHz
f
IN
= 50kHz
f
IN
= 1kHz
f
IN
= 50kHz
69
66
71
69
–75
70
85
82
dB
(1)
dB
dB
dB
dB
dB
Total Harmonic Distortion
Signal-to-Noise Ratio
Spurious Free Dynamic Range
SPECIFICATIONS
ADS7832 Electrical Specifications with 3.3V Supply
V
A
= V
D
= V
REF
+ = 3.3V
±
10%; V
REF
– = AGND = DGND = 0V; CLK = 1MHz external, T
A
= –40
°
C to +85
°
C, after calibration at any temperature, unless otherwise specified.
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PDF描述 |
|---|---|
| ADS7832BP | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7832BP | 功能描述:IC 12-BIT 4CH A/D 28-DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:- |
| ADS7833 | 制造商:BB 制造商全稱(chēng):BB 功能描述:10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| ADS7833N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADS7834 | 制造商:BB 制造商全稱(chēng):BB 功能描述:12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7834_13 | 制造商:BB 制造商全稱(chēng):BB 功能描述:12-Bit High-Speed, Low-Power Sampling ANALOG-TO-DIGITAL CONVERTER |
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