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參數(shù)資料
| 型號(hào)： | ADS7831 |
| 英文描述： | 12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 12位600kHz的采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 10/10頁(yè) |
| 文件大小： | 313K |
| 代理商： | ADS7831 |
10
ADS7831
REFERENCE
REF
REF (pin 3) is the output for the internal 2.5V reference. A
0.1
μ
F capacitor should be connected as close to the REF pin
as possible. The capacitor and the output resistance of REF
create a low pass filter to band limit noise on the reference.
Using a smaller value capacitor will introduce more noise to
the reference degrading the SNR and SINAD. The REF pin
should not be used to drive external AC or DC loads.
CAP
CAP (pin 4) is the output of the internal reference buffer. A
10
μ
F capacitor should be placed as close to the CAP as
possible to provide optimum switching currents for the
CDAC throughout the conversion cycle and compensation
for the output of the buffer. Using a capacitor any smaller
than 2.2
μ
F can cause the output buffer to oscillate and may
not have sufficient charge for the CDAC. Capacitor values
larger than 10
μ
F will have little effect on improving perfor-
mance. The voltage on the CAP pin is approximately 2V
when using the internal reference, or 80% of an externally
supplied reference.
LAYOUT
POWER
The ADS7831 uses the majority of its power for analog and
static circuitry and it should be considered as an analog
component. For optimum performance, tie the analog and
digital +5V power pins to the same +5V power supply and
tie the analog and digital grounds together.
For best performance, the
±
5V supplies can be produced
from whatever analog supply is used for the rest of the
analog signal conditioning. If
±
12V or
±
15V supplies are
present, simple
regulators can be used. The +5V power for
the A/D should be separate from the +5V used for the
system’s digital logic. Connecting V
(pin 27) directly to
a digital supply can reduce converter performance due to
switching noise from the digital logic.
Although it is not suggested, if the digital supply must be used to
power the converter, be sure to properly filter the supply. Either
using a filtered digital supply or a regulated analog supply, both
V
DIG
and V
ANA
should be tied to the same +5V source.
GROUNDING
Three ground pins are present on the ADS7831. DGND
(pin 22) is the digital supply ground. AGND2 (pin 5) is the
analog supply ground. AGND1 (pin 2) is the ground which
all analog signals internal to the A/D are referenced.
AGND1 is more susceptible to current induced voltage
drops and must have the path of least resistance back to the
power supply.
All the ground pins of the ADS should be tied to the
analog ground plane, separated from the system’s digital
logic ground, to achieve optimum performance. Both
analog and digital ground planes should be tied to the
“system” ground as near to the power supplies as possible.
This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common
impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injec-
tion which can cause the driving op amp to oscillate. The
FET switch on the ADS7831, compared to FET switches on
other CMOS A/D converters, releases 5%—10% of the
charge. There is also a resistive front end which attenuates
any charge which is released. The end result is a minimal
requirement for the op amp on the front end. Any op amp
sufficient for the signal in an application will be sufficient to
the drive the ADS7831.
The resistive front end of the ADS7831 also provides a
guaranteed
±
25V over voltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7831 does have tri-state outputs for the parallel
port, but intermediate latches should
be used if the bus will
be active during conversions. If the bus is not active during
conversions, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7831 has an internal LSB size of 610
μ
V.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7831P | 12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7831U | 12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7832 | CMOS Hex Inverting Buffer/Converter 16-SOIC -55 to 125 |
| ADS7832BN | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7832BP | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7831 WAF | 制造商:Texas Instruments 功能描述: |
| ADS7831P | 制造商:Rochester Electronics LLC 功能描述:12-BIT, 600KHZ,SAMPLING A/D - Bulk |
| ADS7831U | 制造商:BB 制造商全稱(chēng):BB 功能描述:12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7832 | 制造商:BB 制造商全稱(chēng):BB 功能描述:Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7832BN | 制造商:Rochester Electronics LLC 功能描述: |
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