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參數(shù)資料
| 型號： | ADS7818EB |
| 英文描述： | 2SC5161 |
| 中文描述： | 2SC5161 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 151K |
| 代理商： | ADS7818EB |
12
ADS7818
D11
(MSB)
DATA
CLK
CONV
D10
D1
D0
(LSB)
2
3
1
4
13
14
15
16
1
2
3
D11
(MSB)
t
ACQ
t
DRP
Input Voltage
(2)
(V)
O
0V
FS = Full-Scale Voltage = 2 V
REF
1 LSB = FS/4096
4.999V
(1)
00...010
00...001
00...000
11...101
11...110
11...111
1 LSB
NOTES: (1) For external reference, value is 2 V
REF
– 1 LSB. (2) Voltage
at converter input: +IN
–
(
–
IN).
FIGURE 7. Ideal Input Voltages and Output Codes.
DSP INTERFACING
Figure 8 shows a timing diagram that might be used with a
typical digital signal processor such as a TI DSP. For the
buffered serial port (BSP) on the TMS320C54X family,
CONV would tied to BFSX, CLK would be tied to BCLKX,
and DATA would be tied to BDR.
SPI/QSPI INTERFACING
Figure 9 shows the timing diagram for a typical serial
peripheral interface (SPI) or queued serial peripheral inter-
face (QSPI). Such interfaces are found on a number of
microcontrollers form various manufacturers. CONV would
be tied to a general purpose I/O pin (SPI) or to a PCX pin
(QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
(master in slave out).
Note the time t
DRP
shown in Figure 9. This represents the
maximum amount of time between CONV going LOW and
the start of the conversion clock. Since CONV going LOW
places the sample and hold in the hold mode and because the
hold capacitor looses charge over time, there is a require-
ment that time t
DRP
be met as well as the maximum clock
period (t
CKP
).
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7818 circuitry. This is particu-
larly true if the CLK input is approaching the maximum
input rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the CLK
input.
FIGURE 8. Typical DSP Interface Timing.
D11
(MSB)
DATA
CLK
CONV
D10
D1
D0
(LSB)
1
2
15
16
3
12
13
14
15
16
1
2
3
4
D11
(MSB)
D10
D9
FIGURE 9. Typical SPI/QSPI Interface Timing.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7818EB/250 | 功能描述:模數(shù)轉換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7818EB/250G4 | 功能描述:模數(shù)轉換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7818EB/2K5 | 功能描述:模數(shù)轉換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7818EB/2K5G4 | 功能描述:模數(shù)轉換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7818EB250 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER |
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