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DESCRIPTION OF SERIAL REGISTERS
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
A7 – A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
00
<RESET>
0
<SERIAL
READOUT>
Software Reset
D7
<RESET>
1 Software reset applied – resets all internal registers and self-clears to 0.
D0
<SERIAL READOUT>
0 Serial readout disabled. SDOUT is forced high or low by the device (and not out in high impedance
state).
1 Serial readout enabled, Pin SDOUT functions as serial data readout. This mode is available only with
CMOS output interface. With LVDS interface, pin 56 becomes CLKOUTM.
A7 – A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
20
0
<ENABLE LOW
0
SPEED MODE>
D2
<ENABLE LOW SPEED MODE>
0 LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS.
1 Enable LOW SPEED mode for sampling frequencies <= 100 MSPS.
A7 – A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
3F
0
<REF>
0
0
<STANDBY>
0
D6-D5
<REF> Internal or external reference selection
01 Internal reference enabled
11 External reference enabled
D1
<STANDBY>
0 Normal operation
1 ADC is powered down for both channels. Internal references, output buffers are active. This results in
quick wake-up time from standby.
Copyright 2009, Texas Instruments Incorporated
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