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參數(shù)資料
| 型號： | ADS5421Y |
| 英文描述： | 14-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 14位，40MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 395K |
| 代理商： | ADS5421Y |
ADS5421
SBAS237D
18
www.ti.com
LAYOUT AND DECOUPLING
CONSIDERATIONS
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high-
frequency designs. Achieving optimum performance with a
fast sampling converter like the ADS5421 requires careful
attention to the PC board layout to minimize the effect of
board parasitics and optimize component placement. A mul-
tilayer board usually ensures best results and allows conve-
nient component placement.
The ADS5421 must be treated as an analog component and
the +V
SA
pins connected to a clean analog supply. This
ensures the most consistent results, because digital supplies
often carry a high level of switching noise that could couple
into the converter and degrade the performance. As men-
tioned previously, the driver supply pins (VDRV) must also
be connected to a low-noise supply. Supplies of adjacent
digital circuits can carry substantial current transients. The
supply voltage must be thoroughly filtered before connecting
to the VDRV supply of the converter. All ground connections
on the ADS5421 are internally bonded to the metal flag
(bottom of package) that forms a large ground plane. All
ground pins must directly connect to an analog ground plane
that covers the PC board area under the converter.
Due to its high sampling frequency, the ADS5421 generates
high-frequency current transients and noise (clock
feedthrough) that are fed back into the supply and reference
lines. If not sufficiently bypassed, this adds noise to the
conversion process. See Figure 15 for the recommended
supply decoupling scheme for the ADS5421. All +V
S
pins
should be bypassed with a combination of 10nF, 0.1
μ
F
ceramic chip capacitors (0805, low ESR) and a 10
μ
F tanta-
lum tank capacitor. A similar approach may be used on the
driver supply pins, VDRV. In order to minimize the lead and
trace inductance, the capacitors must be located as close to
the supply pins as possible. They are best placed directly
under the package where double-sided component mounting
is allowed. In addition, larger bipolar decoupling capacitors
(2.2
μ
F to 10
μ
F), effective at lower frequencies, must also be
used on the main supply pins. They can be placed on the PC
board in proximity (< 0.5") of the ADC.
If the analog inputs to the ADS5421 are driven differentially,
it is especially important to optimize towards a highly sym-
metrical layout. Small trace length differences can create
phase shifts compromising a good distortion performance.
For this reason, the use of two single op amps rather than
one dual amplifier enables a more symmetrical layout and a
better match of parasitic capacitances. The pin orientation of
the ADS5421 package follows a flow-through design with the
analog inputs located on one side of the package whereas
the digital outputs are located on the opposite side of the
quad-flat package. This provides a good physical isolation
between the analog and digital connections. While designing
the layout, it is important to keep the analog signal traces
separated from any digital lines to prevent noise coupling
onto the analog portion.
Try to match trace length for the differential clock signal (if
used) to avoid mismatches in propagation delays. Single-
ended clock lines must be short and should not cross any
other signal traces.
Short circuit traces on the digital outputs will minimize capaci-
tive loading. Trace length must be kept short to the receiving
gate (< 2") with only one CMOS gate connected to one digital
output. If possible, the digital data outputs must be buffered
(with the TI SN74AVC16244, for example). Dynamic perfor-
mance can also be improved with the insertion of series
resistors at each data output line. This sets a defined time
constant and reduces the slew rate that would otherwise flow
due to the fast edge rate. The resistor value may be chosen
to result in a time constant of 15% to 25% of the used data
rate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS5421Y/R | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14 Bit 40MSPS Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5421Y/RG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14 Bit 40MSPS Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5421Y/T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14 Bit 40MSPS Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5421Y/TG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14 Bit 40MSPS Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5422 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-Bit, 62MSPS Sampling ANALOG-TO-DIGITAL CONVERTER |
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