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參數(shù)資料
| 型號(hào)： | ADS5271IPFPT |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 12-Bit, 50MSPS ADC with Serial LVDS Interface |
| 中文描述： | 8通道，12位，50 MSPS的串行LVDS接口模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 537K |
| 代理商： | ADS5271IPFPT |
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SBAS313A JUNE 2004 REVISED JUNE 2004
www.ti.com
13
THEORY OF OPERATION
OVERVIEW
The ADS5271 is an 8-channel, high-speed, CMOS ADC.
It consists of a high-performance sample-and-hold circuit
at the input, followed by a 12-bit ADC. The 12 bits given out
by each channel are serialized and sent out on a single pair
of pins in LVDS format. All eight channels of the ADS5271
operates from a single clock referred to as ADCLK. The
sampling clocks for each of the eight channels are
generated from the input clock using a carefully matched
clock buffer tree. The 12X clock required for the serializer
is generated internally from ADCLK using a phase lock
loop (PLL). A 6X and a 1X clock are also output in LVDS
format along with the data to enable easy data capture.
The ADS5271 operate from internally generated reference
voltages that are trimmed to ensure matching across
multiple devices on a board. This feature eliminates the
need for external routing of reference lines and also
improves matching of the gain across devices. The
nominal values of REF
T
and REF
B
are 2V and 1V,
respectively. These values imply that a differential input of
1V corresponds to the zero code of the ADC, and a
differential input of +1V corresponds to the full-scale code
(4095 LSB). V
CM
(common-mode voltage of REF
T
and
REF
B
) is also made available externally through a pin, and
is nominally 1.5V.
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the digital
error correction logic, ensuring excellent differential
linearity and no missing codes at the 12-bit level. The
pipeline architecture results in a data latency of 6.5 clock
cycles.
The output of the ADC goes to a serializer that operates
from a 12X clock generated by the PLL. The 12 data bits
from each channel are serialized and sent LSB first. In
addition to serializing the data, the serializer also
generates a 1X clock and a 6X clock. These clocks are
generated in the same way the serialized data is
generated, so these clocks maintain perfect synchroniza-
tion with the data. The data and clock outputs of the
serializer are buffered externally using LVDS buffers.
Using LVDS buffers to transmit data externally has
multiple advantages, such as reduced number of output
pins (saving routing space on the board), reduced power
consumption, and reduced effects of digital noise coupling
to the analog circuit inside the ADS5271.
The ADS5271 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
DRIVING THE ANALOG INPUTS
The analog input biasing is shown in Figure 1. The
recommended method to drive the inputs is through AC
coupling. AC coupling removes the worry of setting the
common-mode of the driving circuit, since the inputs are
biased internally using two 600
resistors.
CM Buffer 2
CM Buffer 1
Internal
Voltage
Reference
Input
Circuitry
IN+
IN
V
CM
600
600
ADS5271
Figure 1. Analog Input Bias Circuitry
The sampling capacitor used to sample the inputs is 4pF.
The choice of the external AC coupling capacitor is
dictated by the attenuation at the lowest desired input
frequency of operation. The attenuation resulting from
using a 10nF AC coupling capacitor is 0.04%.
If the input is DC coupled, then the output common-mode
voltage of the circuit driving the ADS5271 should match
the V
CM
(which is provided as an output pin) to within
±
50mV. It is recommended that the output common-mode
of the driving circuit be derived from V
CM
provided by the
device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS5271IPFPTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8Ch 12Bit 40/50MSPS w/Ser LVDS Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5272 | 制造商:BB 制造商全稱:BB 功能描述:8-Channel, 12-Bit, 65MSPS ADC with Serial LVDS Interface |
| ADS5272EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS5272 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS5272IPFP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Channel 65 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5272IPFPG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Channel 65 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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