參數(shù)資料
型號(hào): ADS5270IPFP
英文描述: 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
中文描述: 8通道,12位,40MSPS的ADC的串行LVDS接口
文件頁(yè)數(shù): 14/18頁(yè)
文件大小: 439K
代理商: ADS5270IPFP
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SBAS293D JANUARY 2004 REVISED MAY 2004
www.ti.com
14
The sampling circuit consists of a low-pass RC filter at the
input to filter out noise components that might be getting
differentially coupled on the input pins. The inputs are
sampled on two 4pF capacitors. The sampling on the
capacitors is done with respect to an internally generated
common-mode voltage (INCM). The switches connecting
the sampling capacitors to the INCM are opened out first
(before the switches connecting them to the analog
inputs). This ensures that the charge injection arising out
of the switches opening is independent of the input signal
amplitude to a first-order of approximation. SP refers to a
sampling clock whose falling edge comes an instant
before the SAMPLE clock. The falling edge of SP
determines the sampling instant.
15
IN
1.5pF
SP
SP
SP
(defines sampling instant)
INCM
(internally generated voltage)
INCM
4pF
Sample
15
IN+
1.5pF
1.7pF
4pF
Sample
Figure 2. Input Circuitry
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale input peak-to-peak supported by
the ADS5270 is 2V. For a nominal value of V
CM
(1.5V), IN
P
and IN
N
can swing from 1V to 2V. The ADS5270 is
specially designed to handle an over-voltage differential
peak-to-peak voltage of 4V (2.5V and 0.5V swings on IN
P
and IN
N
). If the input common-mode is not considerably off
from V
CM
during overload (less than 300mV), recovery
from an over-voltage input condition is expected to be
within 4 clock cycles. All of the amplifiers in the SHA and
ADC are specially designed for excellent recovery from an
overload signal.
REFERENCE CIRCUIT DESIGN
The digital beam-forming algorithm relies heavily on gain
matching across all receiver channels. A typical system
would have about 12 octal ADCs on the board. In such a
case, it is critical to ensure that the gain is matched,
essentially requiring the reference voltages seen by all the
ADCs to be the same. Matching references within the eight
channels of a chip is done by using a single internal
reference voltage buffer. Trimming the reference voltages
on each chip during production ensures the reference
voltages are well matched across different chips.
All bias currents required for the internal operation of the
device are set using an external resistor to ground at pin
ISET. Using a 56k
resistor on ISET generates an internal
reference current of 20
μ
A. This current is mirrored
internally to generate the bias current for the internal
blocks. Using a larger external resistor at ISET reduces the
reference bias current and thereby scales down the device
operating power. However, it is recommended that the
external resistor be within 10% of the specified value of
56k so that the internal bias margins for the various blocks
are proper.
Buffering the internal bandgap voltage also generates a
voltage called V
CM
, which is set to the midlevel of REF
T
and REF
B
, and is accessible on a pin. The internal buffer
driving V
CM
has a drive of
±
2mA. It is meant as a reference
voltage to derive the input common-mode in case the input
is directly coupled.
When using the internal reference mode, a resistor greater
than 2
should be added between the reference pins
(REF
T
and REF
B
) and the decoupling capacitor, as shown
in Figure 3.
REF
T
REF
B
0.1
μ
F
2.2
μ
F
> 2
> 2
2.2
μ
F
0.1
μ
F
ADS5270
Figure 3. Internal Refernce Mode
The device also supports the use of external reference
voltages. This mode involves forcing REF
T
and REF
B
externally. In this mode, the internal reference buffer is
tri-stated. Since the switching current for the eight ADCs
come from the externally forced references, it is possible
for the performance to be slightly less than when the
internal references are used. It should be noted that in this
mode, V
CM
and ISET continue to be generated from the
internal bandgap voltage, as in the internal reference
mode. It is therefore important to ensure that the
common-mode voltage of the externally forced reference
voltages matches to within 50mV of V
CM
.
CLOCKING
The eight channels on the chip run off a single ADCLK
input. To ensure that the aperture delay and jitter are same
for all the channels, a clock tree network is used to
generate individual sampling clocks to each channel. The
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