參數(shù)資料
型號(hào): ADS1602IPFBRG4
英文描述: 16-Bit, 2.5MSPS Analog-to-Digital Converter
中文描述: 16位2.5MSPS模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 21/26頁(yè)
文件大?。?/td> 397K
代理商: ADS1602IPFBRG4
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SBAS341B DECEMBER 2004 REVISED APRIL 2005
www.ti.com
21
ANALOG POWER DISSIPATION
An external resistor connected between the RBIAS pin
and the analog ground sets the analog current level, as
shown in Figure 52. The current is inversely proportional
to the resistor value. Table 3 shows the recommended
values of R
BIAS
for different CLK frequencies. Notice that
the analog current can be reduced when using a slower
frequency CLK input because the modulator has more
time to settle. Avoid adding any capacitance in parallel to
R
BIAS
, since this will interfere with the internal circuitry
used to set the biasing.
R
BIAS
RBIAS
AGND
ADS1602
Figure 52. External Resistor Used to Set Analog
Power Dissipation
Table 3. Recommended R
BIAS
Resistor Values for
Different CLK Frequencies
fCLK
16MHz
DATA
RATE
RBIAS
140k
TYPICAL POWER DISSIPATION
WITH REFEN HIGH
1MHz
200mW
24MHz
1.5MHz
100k
270mW
32MHz
2MHz
60k
37k
390mW
40MHz
2.5MHz
530mW
POWER DOWN (PD)
When not in use, the ADS1602 can be powered down by
taking the PD pin low. All circuitry will be shut down,
including the voltage reference. To minimize the digital
current during power down, stop the clock signal supplied
to the CLK input. There is an internal pull-up resistor of
170k
on the PD pin, but it is recommended that this pin
be connected to IOVDD if not used. Make sure to allow
time for the reference to start up after exiting power-down
mode. The internal reference typically requires 15ms.
After the reference has stabilized, allow at least 100
conversions for the modulator and digital filter to settle
before retrieving data.
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