參數(shù)資料
型號(hào): ADS1601IPFBTG4
廠商: Texas Instruments
文件頁數(shù): 13/29頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 1.25MSPS 48-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
視頻文件: Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝: 250
位數(shù): 16
采樣率(每秒): 1.25M
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 380mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,雙極
配用: 296-17825-ND - EVALUATION MODULE FOR ADS1601
0.001
0.0008
0.0006
0.0004
0.0002
0
-
0.0002
-
0.0004
-
0.0006
-
0.0008
-
0.001
0
100
200
300
Frequency(kHz)
400
500
Magnitude(dB)
600
f
=20
CLK
MHz
20
0
-
20
-
40
-
60
-
80
-
100
-
120
-
140
0
10
20
30
40
50
Frequency(MHz)
Magnitude(dB)
60
f
=20
CLK
MHz
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
-
2.5
-
3.0
-
3.5
400
450
500
550
600
Frequency(kHz)
Magnitude(dB)
650
f
=20
CLK
MHz
R
BIAS
RBIAS
AGND
ADS1601
SBAS322D
– DECEMBER 2004 – REVISED OCTOBER 2011
Figure 46. Passband Ripple
Figure 48. Frequency Response Out to 120MHz
ANALOG POWER DISSIPATION
An external resistor connected between the RBIAS
pin and the analog ground sets the analog current
level, as shown in Figure 49. The current is inversely
proportional to the resistor value. Table 3 shows the
recommended values of RBIAS for different CLK
frequencies. Notice that the analog current can be
reduced when using a slower frequency CLK input
because the modulator has more time to settle. Avoid
adding any capacitance in parallel to RBIAS because
this interferes with the internal circuitry used to set
the biasing. Please note that changing RBIAS changes
internally-generated voltages, including the internal
reference; therefore, it should be understood that the
recommendations
of
are
for
external
Figure 47. Passband Transition
reference only.
ANTI-ALIAS REQUIREMENTS
Higher
frequency,
out-of-band
signals
must
be
eliminated to prevent aliasing with ADCs. Fortunately,
the ADS1601 on-chip digital filter greatly simplifies
this filtering requirement. Figure 48 shows the
ADS1601 response out to 60MHz (fCLK = 20MHz).
Since the stop band extends out to 19.3MHz, the
anti-alias filter in front of the ADS1601 only needs to
Figure 49. External Resistor Used to Set Analog
be designed to remove higher frequency signals than
Power Dissipation
this, which can usually be accomplished with a simple
RC circuit on the input driver.
Table 3. Recommended RBIAS Resistor Values for
Different CLK Frequencies
TYPICAL POWER
DATA
DISSIPATION
fCLK
RATE
RBIAS
WITH REFEN HIGH
5MHz
315kSPS
267k
100mW
10MHz
625kSPS
210k
145mW
15MHz
940kSPS
140k
200mW
20MHz
1.25MSPS
60k
325mW
20
Copyright
2004–2011, Texas Instruments Incorporated
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