參數(shù)資料
型號： ADS1259BIPWR
廠商： Texas Instruments
文件頁數(shù)： 16/48頁
文件大小： 0K
描述： IC ADC 24BIT SPI 14KSPS 20TSSOP
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 24
采樣率（每秒）： 14k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極
t
SDSU
t
DSHD
Command
(1)
DRDY
START
or
STOP
t
PWL
START
t
STDR
t
PWH
START
DRDY
STARTPin
Halted
Converting
Command
(1)
START
STOP
or
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
START
When using commands to control conversions, hold
the START pin low. The ADS1259 features two
START is a digital input that controls the ADS1259
modes to control conversions: Gate Control mode
conversions. Conversions are started when START is
and Pulse Control mode. The mode is selected by the
taken high and are stopped when START is taken
PULSE register bit.
low. If START is toggled during a conversion, the
conversion is restarted. DRDY goes high when
Gate Control Mode (PULSE Bit = 0, Default)
START is taken high. Figure 50 andTable 7 show the
START timing.
Conversions begin when either the START pin is
taken high or when the START command is sent.
Note that reasserting START within 22 tCLK cycles of
Conversions continue indefinitely until the START pin
the DRDY falling edge causes DRDY to fall soon
is taken low or the STOP command is transmitted. As
after. This conversion result should be discarded. The
seen in Figure 51, DRDY is forced high when the
next DRDY falling edge, as given in Table 9, is the
conversion starts and falls low when data are ready.
valid conversion data.
When stopped, the conversion in process completes
and further conversions are halted. Figure 50 and
Table 7 show the timing of DRDY and START.
(1) START and STOP commands take effect on the seventh SCLK
falling edge.
Figure 50. START to DRDY Timing
CONVERSION CONTROL
(1) START and STOP opcode commands take effect on the
The conversions of the ADS1259 are controlled by
seventh SCLK falling edge.
either the START pin or by the START command.
Figure 51. Gate Control Mode
Table 7. START Timing (See Figure 50)
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
START pin low or STOP opcode to DRDY setup time to halt further
tSDSU
16
tCLK
conversions
START pin low or STOP opcode hold time to complete current
tDSHD
16
tCLK
conversion (gate mode)
tPWH, L
START pin pulse width high, low
4
tCLK
tSTDR
START pin rising edge to DRDY rising edge
4
tCLK
Copyright
2009–2011, Texas Instruments Incorporated
23
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