參數(shù)資料
型號: ADS1255IDBT
英文描述: Very Low Noise, 24-Bit Analog-to-Digital Converter
中文描述: 極低噪聲,24位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 4/39頁
文件大?。?/td> 427K
代理商: ADS1255IDBT
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
4
ELECTRICAL CHARACTERISTICS (continued)
All specifications at 40
°
C to +85
°
C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Power-Supply
UNIT
MAX
TYP
MIN
AVDD
4.75
5.25
V
DVDD
1.8
3.6
V
μ
A
μ
A
mA
Power-down mode
2
Standby mode
20
AVDD current
Normal mode, PGA = 1, Buffer off
7
10
Normal mode, PGA = 64, Buffer off
16
22
mA
Normal mode, PGA = 1, Buffer on
13
19
mA
Normal mode, PGA = 64, Buffer on
36
50
mA
μ
A
Power-down mode
2
DVDD current
Standby mode, CLKOUT off,
DVDD = 3.3V
95
μ
A
Normal mode, CLKOUT off,
DVDD = 3.3V
0.9
2
mA
Power dissipation
Normal mode, PGA = 1, Buffer off,
DVDD = 3.3V
38
57
mW
Standby mode, DVDD = 3.3V
0.4
mW
Temperature Range
Specified
40
+85
°
C
°
C
°
C
Operating
40
+105
Storage
60
+150
(1)See text for more information on input impedance.
(2)SPS = samples per second.
(3)FSR = full-scale range = 4VREF/PGA.
(4)fCM is the frequency of the common-mode input signal.
(5)Placing a notch of the digital filter at 60Hz (setting fDATA = 60SPS, 30SPS, 15SPS, 10SPS, 5SPS, or 2.5SPS) will further improve the
common-mode rejection of this frequency.
(6)The reference input range with Buffer on is restricted only if self-calibration or gain self-calibration is to be used. If using system calibration or
writing calibration values directly to the registers, the entire Buffer off range can be used.
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ADS1256IDB Very Low Noise, 24-Bit Analog-to-Digital Converter
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