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參數(shù)資料
| 型號： | ADS1252 |
| 英文描述： | 24-Bit, 40kHz ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 24位40kHz的模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 131K |
| 代理商： | ADS1252 |
14
ADS1252
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog Input Differential Voltage—
for an analog signal
that is fully differential, the voltage range can be compared
to that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1252 are at 2.048V, the differential
voltage is 0V. If one analog input is at 0V and the other
analog input is at 4.096V, then the differential voltage
magnitude is 4.096V. This is the case regardless of which
input is at 0V and which is at 4.096V. The digital output
result, however, is quite different. The analog input differen-
tial voltage is given by the following equation:
+V
IN
– –V
IN
A positive digital output is produced whenever the analog
input differential voltage is positive, while a negative digital
output is produced whenever the differential is negative. For
example, a positive full-scale output is produced when the
converter is configured with a 4.096V reference, and the
analog input differential is 4.096V. The negative full-scale
output is produced when the differential voltage is –4.096V.
In each case, the actual input voltages must remain within
the XGND to +V
DD
range.
Actual Analog Input Voltage—
the voltage at any one
analog input relative to GND.
Full-Scale Range (FSR)—
as with most A/D converters, the
full-scale range of the ADS1252 is defined as the “input”
which produces the positive full-scale digital output minus
the “input” which produces the negative full-scale digital
output. For example, when the converter is configured with
a 4.096V reference, the differential full-scale range is:
[4.096V (positive full scale) – (–4.096V) (negative full scale)] = 8.192V
Least Significant Bit (LSB) Weight—
this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
LSBWeight
Full ScaleRange
N
2
=
where N is the number of bits in the digital output.
Conversion Cycle—
as used here, a conversion cycle refers
to the time period between DOUT/DRDY pulses.
Effective Resolution (ER)—
of the ADS1252 in a particular
configuration can be expressed in two different units:
bits rms (referenced to output) and
μ
Vrms (referenced to
input). Computed directly from the converter's output data,
each is a statistical calculation based on a given number of
results. Noise occurs randomly; the rms value represents a
statistical measure which is one standard deviation. The ER
in bits can be computed as follows:
ER in bits rms =
20
log
2
V
Vrms noise
6 02
.
REF
The 2 V
REF
figure in each calculation represents the full-
scale range of the ADS1252. This means that both units are
absolute expressions of resolution—the performance in dif-
ferent configurations can be directly compared, regardless of
the units.
Noise Reduction—
for random noise, the ER can be im-
proved with averaging. The result is the reduction in noise
by the factor
√
N, where N is the number of averages, as
shown in Table IV. This can be used to achieve true 24-bit
performance at a lower data rate. To achieve 24 bits of
resolution, more than 24 bits must be accumulated. A 36-bit
accumulator is required to achieve an ER of 24 bits. The
following uses V
REF
= 4.096V. With the ADS1252 output-
ting data at 40kHz, a 4096 point average will take 102.4ms.
The benefits of averaging will be degraded if the input signal
drifts during that 100ms.
N
NOISE
REDUCTION
FACTOR
ER
IN
ER
IN
(NUMBER
OF AVERAGES)
VRMS
BITS RMS
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
1
31.3
μ
V
22.1
μ
V
15.6
μ
V
11.1
μ
V
7.82
μ
V
5.53
μ
V
3.91
μ
V
2.77
μ
V
1.96
μ
V
1.38
μ
V
978nV
692nV
489nV
18
18.5
19
19.5
20
20.5
21
21.5
22
22.5
23
23.5
24
1.414
2
2.82
4
5.66
8
11.3
16
22.6
32
45.25
64
TABLE IV. Averaging.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS1252U | 24-Bit, 40kHz ANALOG-TO-DIGITAL CONVERTER |
| ADS1252K5 | 24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER |
| ADS1254 | 24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER |
| ADS1254E | 24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER |
| ADS1255IDB | Very Low Noise, 24-Bit Analog-to-Digital Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1252EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1252 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1252K5 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER |
| ADS1252U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252U | 制造商:Texas Instruments 功能描述:IC 24BIT ADC 41.7KSPS SMD |
| ADS1252U/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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