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參數(shù)資料
| 型號： | ADS1226IRGVTG4 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 24-Bit Analog-to-Digital Converter with One- and Two-Channel Differential Inputs and Internal Oscillator |
| 中文描述： | 24位模擬數(shù)字轉(zhuǎn)換器與單和雙通道差分輸入和內(nèi)部振蕩器 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 398K |
| 代理商： | ADS1226IRGVTG4 |
www.ti.com
INTERNAL OSCILLATOR
The ADS1225 and ADS1226 have an internal
oscillator and run without an external crystal or
oscillator.
MODE
The ADS1225 and ADS1226 have two modes of
operation,
allowing
High-Resolution. By taking the MODE pin high, the
data rate is approximately 100Hz with an rms noise
of 15
μ
V. When the MODE pin is low, the ADS1225
and ADS1226 average multiple samples to increase
the noise performance to 4
μ
V of rms noise with a
data rate of 16Hz.
Table 2
shows the MODE pin
operation.
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. First, it
indicates when new data is ready by going LOW.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins to
output the conversion data, most significant bit
(MSB) first. Data is shifted out on each subsequent
SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an
additional SCLK. It then stays high until new data is
ready. This configuration is useful when polling on
the status of DRDY/DOUT to determine when to
begin data retrieval.
START
The START pin provides easy and precise control of
conversions. Pulse the START pin high to begin a
conversion as shown in
Figure 26
and
Table 3
. The
completion of the conversion is indicated by the
DRDY/DOUT pin going low. Once the conversion
completes,
the
ADS1225
automatically shut down to save power. They stay
shut down until START is once again taken high to
begin a new conversion.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each
rising edge. As with CLK, this input may be driven
with 5V logic regardless of the DVDD voltage. There
is hysteresis built into this input, but care should still
be taken to ensure a clean signal. Glitches or
slow-rising signals can cause unwanted additional
shifting. For this reason, it is best to make sure the
rise-and-fall times of SCLK are less than 50ns.
DRDY/DOUT
START
SCLK
ADS1225/6
Status
Shutdown
Conversion Data
Converting
t
CONV
t
START
ADS1225
ADS1226
SBAS346–MAY 2006
for
High-Speed
or
Table 2. MODE Pin Operation for the ADS1225
and ADS1226
MODE PIN
0
1
MODE
DATA RATE
16SPS
100SPS
NOISE
4
μ
Vrms
15
μ
Vrms
High-Resolution
High-Speed
and
ADS1226
Figure 26. Controlling Conversion with the START Pin
Table 3. START Pin Conversion Times for
Figure 26
SYMBOL
t
START
t
CONV
DESCRIPTION
Minimum START pulse to initiate a conversion
Conversion time High-Speed mode
Conversion time High-Resolution mode
MIN
17
8.0
45.5
MAX
UNITS
μ
s
ms
ms
13.3
83.3
13
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