參數(shù)資料
型號(hào)： ADP5041ACPZ-1-R7
廠商： Analog Devices Inc
文件頁數(shù)： 35/40頁
文件大?。?/td> 3581K
描述： IC REG TRPL BCK/LINEAR 20-LFCSP
標(biāo)準(zhǔn)包裝： 1
拓?fù)洌?/td> 降壓（降壓）同步（1），線性（LDO）（2）
功能： 任何功能
輸出數(shù)： 3
頻率 - 開關(guān)： 3MHz
電壓/電流 - 輸出 1： 0.8 V ~ 3.8 V，1.2A
電壓/電流 - 輸出 2： 0.8 V ~ 5.2 V，300mA
電壓/電流 - 輸出 3： 0.8 V ~ 5.2 V，300mA
帶 LED 驅(qū)動(dòng)器： 無
帶監(jiān)控器： 是
帶序列發(fā)生器： 無
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-WQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADP5041ACPZ-1-R7DKR
Data Sheet
ADP5041
 
Rev. 0 | Page 35 of 40
The inductor losses are estimated (without core losses) by
L
RMS
OUT1
L
DCR
I
?/DIV>
E
2
 
(4)
where:
DCRL is the inductor series resistance.
IOUT1(RMS) is the rms load current of the buck regulator.
/12
+
1  r
I
OUT1
RMS
OUT1
?/DIV>
=
 
(5)
where r is the normalized inductor ripple current.
r H VOUT1 ?(1-D)/(IOUT1 ?L ?fSW)
(6)
where:
L is inductance.
fSW is switching frequency.
D is duty cycle.
D = VOUT1/VIN1
(7)
The ADP5041 buck regulator power dissipation, PDBUCK, includes
the power switch conductive losses, the switch losses, and the
transition losses of each channel. There are other sources of
loss, but these are generally less significant at high output load
currents, where the thermal limit of the application is. Equation 8
shows the calculation made to estimate the power dissipation in
the buck regulator.
PDBUCK = PCOND + PSW + PTRAN
(8)
The power switch conductive losses are due to the output current,
IOUT1, flowing through the PMOSFET and the NMOSFET power
switches that have internal resistance, R
DSON-P
 and R
DSON-N
. The
amount of conductive power loss is found by:
P
COND
 = [R
DSON-P
 ?D + R
DSON-N
 ?(1  D)] ?I
OUT1
2
 
(9)
For the ADP5041, at 125癈 junction temperature and VIN1 =
3.6 V , RDSON-P is approximately 0.2 ? and RDSON-N is approximately
0.16 ? At VIN1 = 2.3 V, these values change to 0.31 ?and
0.21 ?respectively, and at VIN1 = 5.5 V, the values are 0.16 ?
and 0.14 ? respectively.
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:
PSW = (CGATE-P + CGATE-N) ?VIN1
2
 ?fSW
(10)
where:
CGATE-P is the PMOSFET gate capacitance.
C
GATE-N
 is the NMOSFET gate capacitance.
For the ADP5041, the total of (C
GATE-P
 + C
GATE-N
) is approximately
150 pF.
The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near VOUT1 (and from VOUT1 to
ground). The amount of transition loss is calculated by:
PTRAN = VIN1 ?IOUT1 ?(tRISE + tFALL) ?fSW
(11)
where tRISE and tFALL are the rise time and the fall time of the
switching node, SW. For the ADP5041, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for
estimating the converter efficiency, it must be noted that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter
performance also depends on the choice of passive components
and board layout; therefore, a sufficient safety margin should be
included in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by:
PDLDO = [(VIN  VOUT) ?ILOAD] + (VIN ?IGND)
(12)
where:
ILOAD is the load current of the LDO regulator.
VIN and VOUT are input and output voltages of the LDO,
respectively.
I
GND
 is the ground current of the LDO regulator.
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the ADP5041 simplifies to:
PD = {[PDBUCK + PDLDO1 + PDLDO2]}
(13)
Junction Temperature
In cases where the board temperature, T
A
, is known, the
thermal resistance parameter, ?/DIV>
JA
, can be used to estimate the
junction temperature rise. TJ is calculated from TA and PD using
the formula
TJ = TA + (PD ??SPAN class="pst ADP5041ACPZ-1-R7_2473529_4">JA)
(14)
The typical ?SPAN class="pst ADP5041ACPZ-1-R7_2473529_4">JA value for the 20-lead, 4 mm ?4 mm LFCSP is
38癈/W (see Table 7). A very important factor to consider is
that ?/DIV>
JA
 is based on a 4-layer, 4 inch ?3 inch, 2.5 oz copper, as
per JEDEC standard, and real applications may use different
sizes and layers. To remove heat from the device, it is important
to maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. The exposed
pad (EP) should be connected to the ground plane with several
vias as shown in Figure 114.
If the case temperature can be measured, the junction temperature
is calculated by
T
J
 = T
C
 + (P
D
 ??/DIV>
JC
)
(15)
where:
TC is the case temperature.
?SPAN class="pst ADP5041ACPZ-1-R7_2473529_4">JC is the junction-to-case thermal resistance provided in
Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5041 power
dissipation (P
D
) due to the losses of all channels by using
Equation 8 to Equation 13. From this power calculation, the
junction temperature, TJ, can be estimated using Equation 14.
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