參數(shù)資料
型號(hào)： ADP3810AR-42
廠商： Analog Devices, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector Cable Assembly; Connector Type A:Circular Receptacle; Connector Type B:Stripped End Leads; Cable Length:10ft RoHS Compliant: Yes
中文描述： 二次側(cè)，離線電池充電器控制器
文件頁(yè)數(shù)： 14/16頁(yè)
文件大?。?/td> 457K
代理商： ADP3810AR-42
ADP3810/ADP3811
–14–
REV. 0
either present or absent. If the battery is present, its large ca-
pacitance creates a very low frequency dominant pole, giving a
single pole system. The more demanding case is when the bat-
tery is removed. Now the output pole is dependent upon the
filter capacitors, C
F1
and C
F2
. This pole is higher in frequency,
and more care must be taken to stabilize the loop response. All
three cases are described in detail below.
The following calculations for compensation components help
to realize stable voltage and current loops. In practical designs,
checking the stability using a network analyzer or a Feedback
Loop Analyzer is always recommended. The calculated compo-
nent values serve as good starting values for a measurement-
based optimization. The component values shown in Figure 23
are slightly different from the calculated values based on this
optimization procedure.
To simplify the analysis further, the loop gain is split into two
components: the gain from the battery to the ADP3810/
ADP3811’s COMP pin and the gain from the COMP pin back
to the battery. Because the compensation of each loop depends
upon the RC network on the COMP pin, it is a convenient
choice for dividing the loop calculations.
Definitions:
Modulator Gain: G
MOD
= gain in dB from the COMP pin to
V
BAT
.
Error Amplifier:
G
EA
= gain in dB from V
BAT
to the COMP pin.
Loop Gain:
G
LOOP
= G
MOD
+ G
EA
.
Modulator Pole: f
PM
, The pole present at the output of the
modulator.
Modulator Zero: f
ZM
, The zero due to the ESR, R
F1
, of the
filter cap, C
F1
.
Voltage Loop Compensation, No Battery
Step 1. Calculate the dc loop gain (G
LOOP
), f
PM
, and f
ZM
:
G
MOD
=
20
×
log
GM
3
×
ITX
OC
×
R
F
×
A
V
2
×
GM
4
×
R
4
[
]
G
MOD
=
20
×
log
6
mA
/
V
×
0.36
×
3.3
k
×
0.333
×
0.091
A
/
V
×
1.2
k
=
48.3
dB
G
EA
=
20
×
log
R
2
R
1
+
R
2
×
GM
2
×
R
5
G
EA
=
20
×
log
20
k
80
k
+
20
k
×
2.1
mA
/
V
×
400
k
=
48.5
dB
G
LOOP
= 44.5
dB
+ 48.3
dB
= 96.8
dB
f
PM
=
1
(
2
π×
R
4
×
C
F
1
+
C
F
2
)
=
1
2
π×
1.2
k
×
1.22
mF
(
)
=
0.11
Hz
f
ZM
=
1
2
π ×
R
F
1
×
C
F
1
=
1
2
π ×
0.1
×
1.0
mF
=
1.6
kHz
In reality, the interaction of C
F1
and C
F2
and their ESRs create
an additional pole/zero pair, but because the value of R
F1
(ESR
of C
F1
) and R
F2
(ESR of C
F2
) are similar, they tend to cancel
each other out. Furthermore, the loop crossover is an order of
magnitude lower in frequency, so the additional pole and zero
have little effect on the loop response.
Step 2. Pick the voltage and current loop crossover frequen-
cies, f
CV
and f
CI
:
To avoid interference between the voltage loop and the current
loop, use f
CV
< 1/10 of f
CI
, the current loop crossover. The cur-
rent loop crossover f
CI
is chosen to be ~ 1.9 kHz to provide a
fast current limiting response time, so pick f
CV
~ 100 Hz.
Step 3. Calculate G
MOD
at f
CV
:
The modulator gain of 46.7 dB is the dc gain. The modulator
pole reduces this gain above f
PM
.
G
MOD
(100
Hz
)
=
G
MOD
(
dc
)
20
×
log 1
+
f
CV
f
PM
2
G
MOD
(100
Hz
)
=
48.3
dB
20
×
log 1
+
100
0.11
2
=
10.9
dB
Step 4. Calculate gain loss of G
EA
at f
CV
:
To have the feedback loop gain cross over 0 dB at f
CV
= 100 Hz,
G
EA
(100 Hz) should be +10.9 dB. Thus, the total gain loss of
G
EA
needed at crossover is:
G
LOSS
=
G
EA
(
dc
) –
G
EA
(100
Hz
) = 48.5
dB
– 10.9
dB
= 37.6
dB
Step 5. Determine f
P
needed to achieve G
LOSS
:
To achieve this G
LOSS
we need to add a pole, which is located at
the COMP pin. GM2 has practically no parasitic loss in
gain at 100 Hz. Its first parasitic pole occurs at approximately
500 kHz as shown in Figure 11. Thus, the entire gain loss must
be realized with an external compensation capacitor, C
C1
, that
sets the pole, f
P1
.
f
P
1
=
f
CV
10
G
LOSS
10
1
=
1.3
Hz
Step 6. Calculate C
C1
based upon f
P
:
C
C
1
=
1
2
π×
R
5
×
f
P
1
≈
0.3
μ
F
Step 7. Calculate the loop phase margin,
F
M
:
The loop phase margin is a combination of the phase of the
modulator pole and zero and the error amplifier pole.
Φ
M
=
180
arc
tan
f
CV
f
P
1
arc
tan
f
CV
f
PM
+
arc
tan
f
CV
f
ZM
≈
0
°
Step 8. Calculate R
C1
to stabilize the loop:
The sum of phase losses of the modulator and error amplifier re-
sults in a loop phase of 0
°
, which is unacceptable for loop stabil-
ity. To stabilize the feedback loop, we have to add a phase
boosting zero to the error amplifier by inserting a resistor (R
C1
)
in series with the capacitor C
C1
. If the desired phase margin is
φ
M
= 60 degrees, the frequency of the zero can be calculated:
f
Z
1
=
f
CV
/tan
φ
M
= 57 Hz
From this, the R
C1
resistor is calculated:
R
C
1
=
1
2
π×
f
Z
1
×
C
C
1
≈
10
k
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