
ADP3808
APPLICATION INFORMATION
DESIGN PROCEDURE
Refer to Figure 16, the typical application circuit, for the
following description. The design follows that of a buck
converter. With Li-Ion cells it is important to have a regulator
with accurate output voltage control.
BATTERY VOLTAGE SETTINGS
Inductor Selection
Usually the inductor is chosen based on the assumption that the
inductor ripple current is ±15% of the maximum output dc
current at maximum input voltage. As long as the inductor used
has a value close to this, the system should work fine. The final
choice affects the trade-offs between cost, size, and efficiency.
For example, the lower the inductance, the size is smaller but
ripple current is higher. This situation, if taken too far, leads to
higher ac losses in the core and the windings. Conversely, a
higher inductance results in lower ripple current and smaller
output filter capacitors, but the transient response will be
slower. With these considerations, the required inductance can
be calculated using Equation 6.
V
V
L1
×
Δ
where the maximum input voltage
V
IN, MAX
is used with the
minimum duty ratio
D
MIN
. The duty ratio is defined as the ratio
of the output voltage to the input voltage, V
BAT
/V
IN
. The ripple
current is calculated using Equation 7.
Δ
I
= 0.3 ×
I
BAT, MAX
The maximum peak-to-peak ripple is 30%, that is 0.3, and
maximum battery current, I
BAT, MAX
, is used.
For example, with V
IN, MAX
= 19 V, V
BAT
= 12.6 V, I
BAT, MAX
= 3A,
and T
S
= 4 μs, the value of L1 is calculated as 18.9 μH. Choosing
the closest standard value gives L1 = 22 μH.
Output Capacitor Selection
An output capacitor is needed in the charger circuit to absorb
the switching frequency ripple current and smooth the output
voltage. The rms value of the output ripple current is given by
(
D
D
fL
12
1
Rev. 0 | Page 14 of 16
S
MIN
BAT
MAX
IN
T
D
I
×
=
,
(6)
(7)
V
I
MAX
IN
rms
=
1
,
)
(8)
The maximum value occurs when the duty cycle is 0.5. Thus,
V
I
MAX
rms
1
072
.
,
_
fL
MAX
IN
=
(9)
For an input voltage of 19 V and a 22 μH inductance, the
maximum rms current is 0.26 A. A typical 10 μF or 22 μF
ceramic capacitor is a good choice to absorb this current.
Input Capacitor Ripple
As is the case with a normal buck converter, the pulse current at
the input has a high rms component. Therefore, because the
input capacitor has to absorb this current ripple, it must have an
appropriate rms current rating. The maximum input rms
current is given by
D
D
D
V
D
η
P
I
IN
BAT
rms
)
1
×
×
=
(10)
where
η
is the estimated converter efficiency (approximately
90%, 0.9) and
P
BAT
is the maximum battery power consumed.
This is a worst-case calculation and, depending on total charge
time, the calculated number could be relaxed. Consult the
capacitor manufacturer for further technical information.
Decoupling the VCC Pin
It is a good idea to use an RC filter (R13 and C14) from the
input voltage to the IC both to filter out switching noise and to
supply bypass to the chip. During layout, this capacitor should
be placed as close to the IC as possible. Values between 0.1 μF
and 2.2 μF are recommended.
Current Sense Filtering
During normal circuit operation, the current sense signals can
have high frequency transients that need filtering to ensure
proper operation. In the case of the CSP and CSM inputs,
Resistor R4 is set to 510 Ω and the filter capacitor C13 is 22 nF.
For the system current sense filter on SYSP, SYSM, R2 is set to
510 Ω, C1 is 2.2 μF, and C2 is 470 nF.
MOSFET Selection
One of the features of the ADP3808 is that it allows use of a
high-side NMOS switch instead of a more costly PMOS device.
The converter also uses synchronous rectification for optimal
efficiency. To use a high-side NMOS, an internal bootstrap
regulator automatically generates a 5.25 V supply
across C9.
Maximum output current determines the R
DS(ON)
requirement
for the two power MOSFETs. When the ADP3808 is operating
in continuous mode, the simplifying assumption can be made
that one of the two MOSFETs is always conducting the load
current. The power dissipation for each MOSFET is given by
Upper MOSFET:
P
DISS
=
R
DS(ON)
× (
I
BAT
× √
D
)
2
+
V
IN
×
I
BAT
× √
D
×
T
SW
×
f
(11)
Lower MOSFET:
P
DISS
=
R
DS(ON)
× (
I
BAT
× √
D
)
2
+
V
IN
× (
I
BAT
× √1
D
)
2
×
t
SW
×
f
where
f
is the switching frequency and
t
SW
is the switch
transition time, usually 10 ns.
The first term accounts for conduction losses while the second
term estimates switching losses. Using these equations and the
manufacturer’s data sheets, the proper device can be selected.
(12)