參數(shù)資料
型號： ADP3806JRU-REEL
廠商： ANALOG DEVICES INC
元件分類： 電源管理
英文描述： High-Frequency Switch Mode Li-Ion Battery Charger
中文描述： 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24
封裝： MO-153AD, TSSOP-24
文件頁數(shù)： 2/16頁
文件大?。?/td> 274K
代理商： ADP3806JRU-REEL
REV. B
–2–
ADP3806–SPECIFICATIONS
1
(@ 0 C
￡
T
A
￡
100 C, VCC = 16 V, unless otherwise noted.)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
BATTERY SENSE INPUT
ADP3806-12.6 V and 16.8 V
ADP3806-12.525 V and 16.7 V
T
A
= 25
∞
C, 13 V
￡
VCC
￡
20 V
5
∞
C
￡
T
A
￡
55
∞
C
0
∞
C
￡
T
A
￡
85
∞
C
Part in Operation
Part in Shutdown
V
BAT
V
BAT
V
BAT
R
BAT
I
BAT(SD)
–0.4
–0.6
–0.7
250
+0.4
+0.6
+0.7
%
%
%
k
W
m
A
Input Resistance
Input Current
350
0.2
1.0
BATTERY SENSE INPUT
ADP3806
V
BAT
= 2.5 V
T
A
= 25
∞
C, 13 V
￡
VCC
￡
20 V
0
∞
C
￡
T
A
￡
85
∞
C
BATSEL = Open, Part in Operation
BATSEL = 100 k
W
to GND, Part in Shutdown
V
BAT
V
BAT
–0.5
–0.7
+0.5
+0.7
1.0
1.0
%
%
m
A
m
A
Input Current Operating
Input Current Shutdown
0.2
0.2
OSCILLATOR
Maximum Frequency
2
Frequency Variation
3
CT Charge Current
0% Duty Cycle Threshold
Maximum Duty Cycle Threshold
SYNC Input High
SYNC Input Low
SYNC Input Current
f
CT
f
CT
I
CT
1000
210
125
kHz
kHz
m
A
V
V
V
V
m
A
CT = 180 pF
250
150
1.0
2.5
290
175
@ COMP Pin
@ COMP Pin
SYNC
H
SYNC
L
I
SYNC
2.2
0.8
1.0
0.2
GATE DRIVE
On Resistance
Rise, Fall Time
Overlap Protection Delay
I
L
= 10 mA
C
L
= 1 nF, DRVL and DRVH
DRVL Falling to DRVH Rising,
DRVH Falling to DRVL Rising
Part in Shutdown, V
SW
= 12.6 V
V
BST
– V
SW
R
ON
t
r
, t
f
t
OP
6
35
50
10
W
ns
ns
SW Bias Current
BST Cap Refresh Threshold
0.2
3.7
1.0
m
A
V
CURRENT SENSE AMPLIFIER
Input Common-Mode Range
Input Differential Mode Range
Input Offset Voltage
5
Gain
5
Input Bias Current
Input Offset Current
Input Bias Current
DRVL Shutdown Threshold
V
CS+
and V
CS–
V
CS4
0 V
￡
V
CS(CM)
￡
VCC
V
CS(CM)
V
CS(DM)
V
CS(VOS)
0.0
0.0
VCC + 0.3
160
V
mV
mV
V/V
m
A
m
A
m
A
mV
1.0
25
50
1.0
0.2
48
0 V
￡
V
CS(CM)
￡
VCC, Part in Operation
0 V
￡
V
CS(CM)
￡
VCC
Part in Shutdown
Measured between V
CS+
and V
CS–
V
CS(IB)
V
CS(IOS)
100
2.0
1.0
V
CS(SD
)
SYSTEM CURRENT SENSE
6
Input Common-Mode Range
Input Differential Range
Input Offset Voltage
Input Bias Current, SYS+
Input Bias Current, SYS–
Voltage Gain
Output Range
Limit Output Threshold
Limit Output Voltage
SYS+ and SYS–, I
L
= 0 mA, V
ISYS
= 3 V
(V
SYS+
) – (V
SYS–
)
V
SYS(CM)
V
SYS(DM)
4.0
0
VCC + 0.3
100
V
mV
mV
m
A
m
A
V/V
V
V
V
0.5
200
70
50
V
SYS(DM)
= 0 V, V
SYS(CM)
= 16 V
V
SYS(DM)
= 0 V, V
SYS(CM)
= 16 V
10 V
￡
V
SYS(CM)
￡
VCC + 0.3 V, I
L
= 100
m
A
I
L
= 1 mA
7
, V
SYS(CM)
> 6 V
V
LIMIT
￡
0.2 V, 50 k
W
Pull-up to 5 V
V
ISYS
> 2.65 V, I
SINK
= 700
m
A
I
B(SYS+)
I
B(SYS–)
300
125
51.5
5.0
2.7
0.2
48.5
0
2.3
V
ISYS
V
TH(LIMIT)
V
O(LIMIT)
2.5
0.1
ISET INPUT
Charge Current Programming
Function
Programming Function Accuracy
0.0 V < V
ISET
￡
4.0 V
V
ISET
= 4.0 V, 1 V
￡
V
CS(CM)
￡
16 V
V
ISET
= 0.50 V, 1 V
￡
V
CS(CM)
￡
10 V
5
∞
C
￡
T
A
￡
55
∞
C, V
ISET
= 206 mV,
V
CS(CM)
= 5 V and 10 V
0.0 V
￡
V
ISET
￡
4.0 V
V
ISET/VCS
25
±
1.0
±
10
V/V
%
%
%
–5
–30
–46.7
+5
+30
+33
ISET Bias Current
I
B
0.2
1.0
m
A
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