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參數(shù)資料
| 型號： | ADP3804JRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.50V) 8-TSSOP -40 to 110 |
| 中文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 89K |
| 代理商： | ADP3804JRU |
ADP3804
–6–
REV. PrI
TECHNICAL
DATA
BST and SW is typically 6 V.
T he DRVL pin switches between BST REG and PGND. T he 7
V output of BST REG drives the external NMOS with high
VGS to lower the ON resistance. PGND should be connected
close to the source pin of the external synchronous NMOS.
When DRVL is high, this turns on the lower NMOS and pulls
the SW node to ground. At this point, the boost capacitor is
charged up through the internal boost diode. When the PWM
switches high, DRVL is turned off and DRVH turns on.
DRVH switches between BST and SW. When DRVH is on,
the SW pin is pulled up to the input supply (typically 16 V),
and BST rises above this voltage by approximately 6 V.
Overlap protection is included in the driver to ensure that both
external MOSFET s are not on at the same time. When DRVH
turns off the upper MOSFET , the SW node goes low due to
the inductor current. T he ADP3804 monitors the SW voltage,
and turns on DRVL when SW goes below 1 V. If, under low
current loads, the SW voltage does not drop below 1 V, DRVL
will turn on after time-out of 200 nsec. When DRVL turns off,
an internal timer adds a delay of 50 nsec before turning DRVH
on.
T ypical values of R
CS
are in the range from 25 m to 50 m ,
and the input range of ISET is from 0 V to 4 V. If, for example,
a 2 A charger is required, then R
CS
could be set to 50 m and
V
ISET
= 2.5 V. T he power dissipation in R
CS
should be kept
below 500 mW. In this example, the power is a maximum of
200 mW. Once R
CS
has been chosen, the charge current can be
adjusted during operation with V
ISET
. Lowering V
ISET
to
125 mV gives a charge current of 100 mA for trickle charging.
Components R3, R4, and C13 provide high frequency filtering
for the current sense signal.
F inal Battery Voltage C ontrol
As the battery approaches its final voltage, the ADP3804
switches from CC mode to CV mode. T he change is achieved
by the common output node of g
m1
and g
m2
. Only one of the
two outputs controls the voltage at the COMP pin. Both ampli-
fiers can only pull down on COMP, such that when either
amplifier has a positive differential input voltage, its output is
not active. For example, when the battery voltage, V
BAT
, is low,
g
m2
does not control V
COMP
. When the battery voltage reaches
the desired final voltage, g
m2
takes control of the loop, and the
charge current is reduced.
Amplifier g
m2
compares the battery voltage to the internal refer-
ence voltage of 2.5 V. In the case of the ADP3804-12.5 and
ADP3804-12.6, an internal resistor divider sets the final battery
voltage to 12.6 V. In contrast, the ADP3804 requires external,
precision resistors. T he divider ratio should be set to divide the
desired final voltage down to 2.5 V at the BAT pin:
11
12
1
2.5
BAT T ERY
V
R
R
V
(2)
T hese resistors should be high impedance to limit the battery
leakage current. Alternatively, an external NMOS can be added
in series with R12 to turn off during shutdown. In the case of
the ADP3804-12.5 and ADP3804-12.6, an internal MOSFET
disconnects the internal divider to reduce the leakage current
into BAT to less than 1 μA during shutdown. If the ADP3804-
12.5 or ADP3804-12.6 is used, then R11 should be shorted
and R12 open. T he reference and internal resistor divider are
referenced to the AGND pin, which should be connected close
to the negative terminal of the battery to minimize sensing
errors.
F inal Battery Voltage Adjust
T he ADJ pin provides an analog input to adjust the final bat-
tery voltage by ± 5%. Figure 2 shows the control curve for this
amplifier. Above the threshold voltage of 4.6 V, the amplifier is
turned off. T hus, to disable this function, ADJ should be con-
nected to REG. In the linear range between 1 V and 4 V, the
percentage change in V
BAT
is a function V
ADJ
as follows:
2.5
%
100
30
ADJ
BAT
V
V
V
(3)
T his percent change is the same for the ADP3804 (2.5 V out-
put) and the ADP3804-12.6.
Oscillator and PWM
T he oscillator generates a triangle waveform between 1 V and
2.5 V, which is compared to the voltage at the COMP pin,
setting the duty cycle of the driver stage. When V
COMP
is below
1 V, the duty cycle is zero. Above 2.5 V, the duty cycle reaches
its maximum. T he ADP3804 forces a minimum off time of
approximately 200 nsec to ensure that the boost capacitor is
always charged. T his off time sets the maximum duty cycle.
For example, a 200 kHz frequency (5 μsec period) gives a
maximum duty cycle of 96%.
T he oscillator frequency is set by the external capacitor at the
CT pin and the internal current source of 150 μA according to
the following formula:
150
CT
2
1.5
OSC
f
A
V
(4)
A 200 pF capacitor sets the frequency to 250 kHz. T he fre-
quency can also be synchronized to an external oscillator by
applying a square wave input on SYNC. T he SYNC function is
designed to allow only increases in the oscillator frequency.
T he f
SYNC
should be no more than 20% higher than f
OSC
. T he
duty cycle of the SYNC input is not important and can be
anywhere between 5% and 95%.
7V Boost Regulator
T he driver stage is powered by the internal 7V boost regulator,
which is available at the BST REG pin. Because the switching
currents are supplied by this regulator, decoupling must be
added. A 0.1 μF capacitor should be placed close to the
ADP3804, with the ground side connected close to the power
ground pin, PGND. T his supply is not recommended for use
externally due to high switching noise.
Boosted Synchronous Driver
T he PWM comparator controls the state of the synchronous
driver. A high output from the PWM comparator forces DRVH
proximately 5 for fast rise and fall times when driving exter-
nal MOSFET s. Furthermore, the boosted drive allows an
external NMOS transistor for the main switch instead of a
PMOS. A boost diode is internally connected between
BST REG and BST , and a boost capacitor of 0.1 μF must be
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