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參數(shù)資料
| 型號： | ADP3610ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.45V) 8-TSSOP |
| 中文描述： | SWITCHED CAPACITOR CONVERTER, 650 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ADP3610ARU |
REV. A
ADP3610
–6–
THEORY OF OPERATION
The ADP3610 is an unregulated switched capacitor voltage
doubler that provides an output voltage greater than 5.4 V from
a +3.0 V to +3.6 V input. The unique push-pull voltage dou-
bling architecture allows it to deliver a maximum of 320 mA
output current. A typical application circuit, as shown in Figure
20, requires five small external capacitors. The ADP3610 has an
internal 1 MHz oscillator that is divided by two and used to
generate two nonoverlapping phase clocks.
The basic principle behind a conventional switched capacitor
voltage doubler is shown in Figure 15. During phase one, S1
and S2 are ON, charging the pump capacitor to the input volt-
age. In phase two, switches S1 and S2 are turned OFF and S3
and S4 are turned ON. During phase two, the pump capacitor
is placed in series with the input voltage, thereby charging the
output capacitor to the sum of input voltage and pump ca-
pacitor voltage, resulting in voltage doubling at the output
terminal.
+
S2
S1
V
IN
V
OUT
S3
S4
C
P
f
A
PHASE
1
PHASE
2
f
B
f
B
f
A
f
A
f
B
Figure 15. Conventional Voltage Doubler Configuration
The ADP3610 has two sets of switched capacitor voltage dou-
blers connected in parallel delivering charge to the output as
shown in Figure 16.
+
V
IN
V
OUT
S8
f
B
f
A
CP2
S6
S7
S2
S3
f
A
f
A
f
B
CP1
+
S5
S4
S1
f
B
f
B
f
A
Figure 16. Switch Configuration Charging the Pump
Capacitor
The two voltage doublers run in opposite phases, i.e., when one
pump capacitor is being charged, the other is charging the out-
put, as shown in Figure 17. In this architecture, one of the
pump capacitors is always delivering charge to the output. As a
result, output ripple is at a frequency that is double the switch-
ing frequency. This allows the use of a smaller output capacitor
compared to a conventional voltage doubler.
PHASE 1
(a)
V
IN
V
OUT
S8
CP2
S6
S7
S2
CP1
f
A
f
A
f
A
+
+
S3
f
B
S4
f
B
S5
f
B
f
B
S1
f
A
PHASE 2
(b)
f
B
S6
S3
S5
S4
f
B
V
OUT
+
+
CP1
S2
CP2
V
IN
f
B
f
B
S8
f
A
S1
f
A
f
A
f
A
S7
Figure 17. (a) Phase 1 “Push” Charging
(b) Phase 2 “Pull” Charging
Overvoltage Protection
The input voltage is scaled with a resistor network and com-
pared to the bandgap reference voltage of 1.25 V by a 50 mV
hysteresis comparator. When the input voltage exceeds 4.0 V,
the overvoltage protection signal stops the oscillator.
R1
R2
ADP3610
BANDGAP
= 1.25V
V
IN
OSC
EN
50mV
Figure 18. Overvoltage Protection
Shutdown Mode
The ADP3610’s output can be disabled by pulling the SD pin
high to a TTL/CMOS logic compatible level which will stop the
internal oscillator. In shutdown mode, all analog circuitry in-
cluding overvoltage protection is shut off, thereby reducing the
quiescent current to 10
μ
A typical. Applying a digital low level
or tying the SD pin to ground will turn on the output. If the
shutdown feature is not used, SD pin should be tied to the
ground pin. The output voltage in shutdown mode is approxi-
mately V
IN
– 0.6 V.
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