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參數(shù)資料
| 型號： | ADP3418 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Bootstrapped 12 V MOSFET Driver with Output Disable |
| 中文描述： | 12伏雙自舉MOSFET驅(qū)動器與輸出禁用 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 224K |
| 代理商： | ADP3418 |
REV. 0
ADP3418
–7–
THEORY OF OPERATION
The ADP3418 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.
A more detailed description of the ADP3418 and its features
follows. Refer to the Functional Block Diagram.
Low-Side Driver
The low-side driver is designed to drive a ground-referenced
low R
DS(ON)
N-channel MOSFET. The bias to the low-side
driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180
°
out of
phase with the PWM input. When the ADP3418 is disabled, the
low-side gate is held low.
High-Side Driver
The high-side driver is designed to drive a floating low R
DS(ON)
N-channel MOSFET. The bias voltage for the high-side driver
is developed by an external bootstrap supply circuit, which is
connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C
BST
. When the ADP3418 is starting up, the SW pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high-side
driver will begin to turn on the high-side MOSFET, Q1, by
pulling charge out of C
BST
. As Q1 turns on, the SW pin will rise
up to V
IN
, forcing the BST pin to V
IN
+ V
C(BST)
, which is enough
gate-to-source voltage to hold Q1 on. To complete the cycle,
Q1 is switched off by pulling the gate down to the voltage at the
SW pin. When the low-side MOSFET, Q2, turns on, the SW
pin is pulled to ground. This allows the bootstrap capacitor to
charge up to VCC again.
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.
Overlap Protection Circuit
The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on-off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from Q1’s
turn-off to Q2’s turn-on and by internally setting the delay from
Q2’s turn-off to Q1’s turn-on.
To prevent the overlap of the gate drives during Q1’s turn-off
and Q2’s turn-on, the overlap circuit monitors the voltage at the
SW pin. When the PWM input signal goes low, Q1 will begin to
turn-off (after a propagation delay), but before Q2 can turn on,
the overlap protection circuit waits for the voltage at the SW pin
to fall from V
IN
to 1 V. Once the voltage on the SW pin has
fallen to 1 V, Q2 will begin turn-on. By waiting for the voltage on
the SW pin to reach 1 V, the overlap protection circuit ensures
that Q1 is off before Q2 turns on, regardless of variations in
temperature, supply voltage, gate charge, and drive current.
To prevent the overlap of the gate drives during Q2’s turn-off
and Q1’s turn-on, the overlap circuit provides an internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn off (after a propagation delay), but before Q1
can turn on, the overlap protection circuit waits for the voltage
at DRVL to drop to around 10% of V
CC
. Once the voltage at
DRVL has reached the 10% point, the overlap protection circuit
will wait for a 20 ns typical propagation delay. Once the delay
period has expired, Q1 will begin turn-on.
APPLICATION INFORMATION
Supply Capacitor Selection
For the supply input (V
CC
) of the ADP3418, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 4.7
μ
F, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size. Keep the ceramic
capacitor as close as possible to the ADP3418.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (C
BST
) and
a diode, as shown in Figure 1. Selection of these components
can be done after the high-side MOSFET has been chosen.
The bootstrap capacitor must have a voltage rating that is able
to handle twice the maximum supply voltage. A minimum 50 V
rating is recommended. The capacitance is determined using
the following equation
Q
V
BST
where
Q
GATE
is the total gate charge of the high-side MOSFET,
and
V
BST
is the voltage droop allowed on the high-side MOSFET
drive. For example, an IPD30N06 has a total gate charge of
about 20 nC. For an allowed droop of 200 mV, the required
bootstrap capacitance is 100 nF. A good quality ceramic capaci-
tor should be used.
A small-signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by V
CC
. The bootstrap diode
must have a minimum 15 V rating to withstand the maximum
supply voltage. The average forward current can be estimated by
I
where
f
MAX
is the maximum switching frequency of the control-
ler. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 12 V
supply and the ESR of C
BST
.
C
BST
GATE
=
(1)
Q
f
F AVG
GATE
MAX
)
=
×
(2)
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