VDD = 3.0 V to 3.6 V, C
參數(shù)資料
型號： ADN4668ARUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 7/12頁
文件大?。?/td> 0K
描述： IC RCVR LVDS DIFF 4CH 16TSSOP
標準包裝： 1,000
類型： 線路接收器
驅(qū)動器/接收器數(shù)： 0/4
規(guī)程： LVDS
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
ADN4668
Rev. A | Page 4 of 12
AC CHARACTERISTICS
VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1, 2, 3, 4
Table 2.
Parameter5
Min
Typ
Max
Unit
Conditions/Comments6
Differential Propagation Delay, High-to-Low, tPHLD
1.2
2.0
2.7
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Differential Propagation Delay, Low-to-High, tPLHD
1.2
1.9
2.7
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Differential Pulse Skew |tPHLD tPLHD|, tSKD18
0
0.1
0.4
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Differential Channel-to-Channel Skew, Same Device, tSKD23
0
0.15
0.5
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Differential Part-to-Part Skew, tSKD34
1.0
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Differential Part-to-Part Skew, tSKD49
1.5
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Rise Time, tTLH
0.5
1.0
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Fall Time, tTHL
0.35
1.0
ns
CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3
Disable Time, High-to-Z, tPHZ
8
14
ns
RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5
Disable Time, Low-to-Z, tPLZ
8
14
ns
RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5
Enable Time, Z-to-High, tPZH
9
14
ns
RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5
Enable Time, Z-to-Low, tPZL
9
14
ns
RL = 2 kΩ, CL = 15 pF,7 see Figure 4 and Figure 5
Maximum Operating Frequency, fMAX10
200
250
MHz
All channels switching
1 All typicals are given for VCC = 3.3 V and TA = 25°C.
2 Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, and tR and tF (0% to 100%) ≤ 3 ns for RINx+/RINx.
3 Channel-to-channel skew, tSKD2, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on
the inputs.
4 Part-to-part skew, tSKD3, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of
each other within the operating temperature range.
5 AC parameters are guaranteed by design and characterization.
6 Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified.
7 CL includes probe and jig capacitance.
8 tSKD1 is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel.
9 Part-to-part skew, tSKD4, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended
operating temperature and voltage ranges and across process distribution. tSKD4 is defined as |maximum minimum| differential propagation delay.
10 fMAX generator input conditions: f = 200 MHz, tR = tF < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V p-p to 1.35 V p-p). Output criteria: 60%/40% duty cycle,
VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), CL = 15 pF (stray plus probes).
TEST CIRCUITS AND WAVEFORMS
SIGNAL
GENERATOR
RECEIVER
IS ENABLED
RINx+
RINx–
CL
CL = LOAD AND TEST JIG CAPACITANCE
VCC
ROUTx
50
07
23
7-
0
02
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
80%
20%
1.5V
20%
1.5V
tPLHD
tPHLD
RINx–
RINx+
0V (DIFFERENTIAL)
tTLH
tTHL
VOH
VOL
1.2V
1.3V
1.1V
ROUTx
VID = 200mV
07
23
7-
0
03
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
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