參數(shù)資料
型號: ADN4665ARUZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: IC DRIVER DIFF LVDS QUAD 16TSSOP
標(biāo)準(zhǔn)包裝: 1,000
類型: 線路驅(qū)動器,發(fā)射器
驅(qū)動器/接收器數(shù): 4/0
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
3 V, LVDS, Quad, CMOS
Differential Line Driver
ADN4665
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2009 Analog Devices, Inc. All rights reserved.
FEATURES
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
100 ps typical differential skew
400 ps maximum differential skew
2 ns maximum propagation delay
3.3 V power supply
±350 mV differential signaling
Low power dissipation (13 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range: 40°C to +85°C
Available in surface-mount SOIC package and low profile
TSSOP package
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
FUNCTIONAL BLOCK DIAGRAM
DOUT1+
DOUT1–
DOUT2+
DOUT2–
DOUT3+
DOUT4+
DIN4
DOUT4–
DOUT3–
DIN1
DIN2
DIN3
VCC
EN
GND
ADN4665
D1
EN
D4
D2
D3
08
5-
0
01
Figure 1.
GENERAL DESCRIPTION
The ADN4665 is a quad-channel, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±3.5 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typi-
cally ±350 mV across a termination resistor at the receiving end.
This voltage is converted back to a TTL/CMOS logic level by an
LVDS receiver.
The ADN4665 also offers active high and active low enable/
disable inputs (EN and EN). These inputs control all four drivers
and turn off the current outputs in the disabled state to reduce
the quiescent power consumption to typically 10 mW.
The ADN4665 offers a new solution to high speed, point-to-point
data transmission and offers a low power alternative to emitter-
coupled logic (ECL) or positive emitter-coupled logic (PECL).
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