參數資料
| 型號： | ADN2818ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 23/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘和數據恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 788 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Data Sheet
ADN2817/ADN2818
Rev. E | Page 3 of 40
REVISION HISTORY
1/13 Rev. D to Rev. E
Moved Revision History Section.....................................................3
Change to Table 8............................................................................15
Changes to Table 15 ........................................................................17
Changes to Rate Selectivity Section ..............................................28
1/12—Rev. C to Rev. D
Changes to Figure 14 ......................................................................12
Updated Outline Dimensions........................................................37
3/10—Rev. B to Rev. C
Changes to Features Section and Applications Section ...............1
Changes to Thermal Resistance Section ........................................9
Added Table 6; Renumbered Sequentially.....................................9
Changes to Table 7 ..........................................................................10
Changes to Table 8 ..........................................................................14
Changes to Table 14 ........................................................................15
Deleted Table 16; Renumbered Sequentially...............................16
Changes to Table 16 ........................................................................16
Changes to I2C Interface Section...................................................24
Changed fREF Ratio to DIV_FREF Ratio.......................................25
Changes to Initiate Frequency Acquisition, Rate Selectivity,
Double Data Rate Mode, and PRBS Generator/Detector
Sections.............................................................................................27
Changes to Table 19 ........................................................................32
Changes to Table 20 ........................................................................34
2/09—Rev. A to Rev. B
Updated Outline Dimensions........................................................37
Changes to Ordering Guide...........................................................37
8/08—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Figure 1...............................................................................................1
Added Bit Rate Monitor Specifications Section and Table 4;
Renumbered Sequentially ................................................................7
Changes to Figure 5 and Table 6 ...................................................10
Changes to Table 7 and Table 8 .....................................................14
Changes to Table 14 ........................................................................15
Added Table 15................................................................................15
Added Table 16................................................................................16
Added Sample Phase Adjust Section and Bit Error Rate (BER)
Monitor Section...............................................................................23
Added Figure 32; Renumbered Sequentially...............................24
Changes to Figure 36 ......................................................................29
Added Exposed Pad Notation to Outline Dimensions..............37
7/07—Revision 0: Initial Version
相關PDF資料 |
PDF描述 |
|---|---|
| XRT91L31IQ-F | IC TXRX SONET/SDH 8BIT 64QFP |
| MS27496E19A32S | CONN RCPT 32POS BOX MNT W/SCKT |
| AD9548BCPZ | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| V375C36M150BL3 | CONVERTER MOD DC/DC 36V 150W |
| MAX3676EHJ+ | IC CLOCK RECOVERY 32-TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADN2818ACPZ-RL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs |
| ADN2818ACPZ-RL7 | 功能描述:IC CLOCK/DATA RECOVERY 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| ADN2819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復。