參數(shù)資料
型號(hào)： ADMC401BST
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Single-Chip, DSP-Based High Performance Motor Controller
中文描述： 24-BIT, 13 MHz, OTHER DSP, PQFP144
封裝： PLASTIC, LQFP-144
文件頁(yè)數(shù)： 15/60頁(yè)
文件大?。?/td> 417K
代理商： ADMC401BST
ADMC401
–15–
REV. B
BUS
EXCHANGE
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
14
14
24
16
6
R BUS
16
COMPANDING
CIRCUITRY
DMA BUS
PMA BUS
DMD BUS
PMD BUS
PROGRAM
SEQUENCER
INSTRUCTION
REGISTER
INPUT REGS
OUTPUT REGS
SHIFTER
INPUT REGS
OUTPUT REGS
MAC
INPUT REGS
OUTPUT REGS
ALU
SERIAL
PORT 0
RECEIVE REG
TRANSMIT REG
CONTROL
LOGIC
DM RAM
1K 16
PM ROM
2K 24
PM RAM
2K 24
SERIAL
PORT 1
RECEIVE REG
TRANSMIT REG
5
TIMER
BOOT
ADDRESS
GENERATOR
14
24
2
POWER DOWN
CONTROL
LOGIC
EXTERNAL
DATA BUS
EXTERNAL
ADDRESS BUS
Figure 10. DSP Core Block Diagram
ARCHITECTURE OVERVIEW
Figure 10 is a functional block diagram of the DSP core of the
ADMC401. The DSP core is based on the fixed-point ADSP-
2171 core that is a member of the fixed-point ADSP-21xx
family of general purpose DSPs from Analog Devices Inc.
The ADSP-2171 flexible architecture and comprehensive in-
struction set allow the processor to perform multiple operations
in parallel.
In one processor cycle (38.5 ns with a 13 MHz crystal) the DSP
core can:
Generate the next program address.
Fetch the next instruction.
Perform one or two data moves.
Update one or two data address pointers.
Perform a computational operation.
This all takes place while the ADMC401 continues to:
Receive and transmit through the serial ports.
Decrement the interval timers.
Generate PWM signals.
Convert the ADC input signals.
Operate the encoder interface unit.
Operate all other peripherals including the auxiliary PWM and
event timer subsystem.
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, multiply/
subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormal-
ization and derive exponent operations. The shifter can be used
to implement numeric format control efficiently, including
floating-point representations. The internal result (R) bus di-
rectly connects the computational units so that the output of
any unit may be the input of any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC401 executes looping code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
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