參數(shù)資料
型號(hào)： ADMC401
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Single-Chip, DSP-Based High Performance Motor Controller
中文描述： 24-BIT, 13 MHz, OTHER DSP, PQFP144
封裝： TQFP-144
文件頁數(shù)： 27/60頁
文件大小： 417K
代理商： ADMC401
ADMC401
–27–
REV. B
The SENSE pin controls whether the A/D system operates with
an internal or an external reference. For operation with the internal
reference, the SENSE pin should be tied to the REFCOM pin.
In this mode, the internally derived 2 V voltage reference ap-
pears at the V
REF
pin. To operate with an external voltage refer-
ence, the SENSE pin should be tied to the AV
DD
pin and the
external voltage reference may be applied at the V
REF
pin.
REFCOM
SENSE
0.1 F
CML
CAPB
ADMC401
CAPT
V
REF
0.1 F
0.1 F
10 F
0.1 F
0.1 F
10 F
Figure 20. Recommended Capacitor Decoupling Networks
for the ADMC401
OPTIMIZING ADC PERFORMANCE
The optimum noise and dc linearity performance is achieved
with the largest input signal voltage span (i.e., 4 V input span)
and with matching impedance in series with each of the analog
inputs (VIN0 to VIN7, ASHAN and BSHAN). Additionally,
the operational amplifier must exhibit source impedance that is
both low and resistive, up to and beyond the sampling frequency.
When a capacitive load is switched onto the output of the opera-
tional amplifier, the output will momentarily drop, due to its
effective output impedance. As the output recovers, ringing may
occur. To remedy this situation, a series resistor can be inserted
between the op amp output and the ADC input (R
S
as shown in
Figure 18). Recommended configurations include using the
OP27 amplifiers with an R
S
of 20
. Alternative recommended
op amps are the AD8051 and AD8054.
Figure 18 shows ASHAN driven by the internally generated
reference voltage at V
REF
. When driving ASHAN with an inter-
nally generated V
REF
, better performance will result if the driv-
ing impedance of ASHAN matches the driving impedance of the
other analog inputs. This can be implemented with the addition
of a second amplifier to Figure 18, between V
REF
and ASHAN,
to match the amplifier on VIN0.
For noise sensitive applications, it may also be beneficial to add
some shunt capacitance between the inputs (VIN0 and ASHAN
of Figure 18) and analog ground. Since this additional capaci-
tance combines with the equivalent input capacitance of the
analog inputs, a lower series resistance may be possible. The
input RC combination also provides some antialiasing filtering
on the analog inputs. To optimize performance when noise is
the primary consideration, increase the shunt capacitance as
much as the transient response of the input signal will allow.
Increasing the capacitance too much may adversely affect the
op amp’s settling time, frequency response and distortion
performance.
ADC REGISTERS
The configuration and structure of the ADC registers is de-
scribed at the end of this data sheet.
THE PWM CONTROLLER
OVERVIEW
The PWM generator block of the ADMC401 is a flexible, pro-
grammable, three-phase PWM waveform generator that can be
programmed to generate the required switching patterns to drive
a three-phase voltage source inverter for ac induction (ACIM)
or permanent magnet synchronous (PMSM) motor control. In
addition, the PWM block contains special functions that consid-
erably simplify the generation of the required PWM switching
patterns for control of the electronically commutated motor
(ECM) or brushless dc motor (BDCM). A special mode for
switched reluctance motors (SRM) exists as well, enabled by a
dedicated pin.
The PWM generator produces three pairs of PWM signals on
the six PWM output pins (AH, AL, BH, BL, CH and CL). The
six PWM output signals consist of three high side drive signals
(AH, BH and CH) and three low side drive signals (AL, BL and
CL). The polarity of the generated PWM signals may be pro-
grammed by the PWMPOL pin, so that either active HI or
active LO PWM patterns can be produced by the ADMC401.
The switching frequency, dead time and minimum pulsewidths
of the generated PWM patterns are programmable using respec-
tively, the PWMTM, PWMDT and PWMPD registers. In addi-
tion, three duty-cycle control registers (PWMCHA, PWMCHB
and PWMCHC) directly control the duty cycles of the three
pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low-
side output and the signal destined for the low side switch is
diverted to the corresponding high side output signal. In addi-
tion to ease of use of the PWM controller for ECM or BDCM,
this crossover mode can also be used to transition the PWM
signals into the overmodulation range with relative ease.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation tech-
niques, optical isolation using opto-isolators and transformer
isolation using pulse transformers. The PWM controller of the
ADMC401 permits mixing of the output PWM signals with a
high-frequency chopping signal to permit easy interface to such
pulse transformers. The features of this gate-drive chopping
mode can be controlled by the PWMGATE register. There is an
8-bit value within the PWMGATE register that directly controls
the chopping frequency. In addition, high frequency chopping
can be independently enabled for the high side and the low side
outputs using separate control bits in the PWMGATE register.
Also, all PWM outputs have sufficient sink and source capability
to directly drive most opto-isolators.
The PWM generator is capable of operating in two distinct
modes, single update mode or double update mode. In single
update mode the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are sym-
metrical about the midpoint of the PWM period. In the double
update mode, a second updating of the PWM registers is imple-
mented at the midpoint of the PWM period. In this mode, it is
possible to produce asymmetrical PWM patterns that produce
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