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參數(shù)資料
| 型號(hào)： | ADM693AARW |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Microprocessor Supervisory Circuits |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 337K |
| 代理商： | ADM693AARW |
ADM691A/ADM693A/ADM800L/M
–11–
REV. 0
RAM Write Protection
The
CE
OUT
line drives the Chip Select inputs of the CMOS
RAM.
CE
OUT
follows
CE
IN
as long as V
CC
is above the reset
threshold. If V
CC
falls below the reset threshold,
CE
OUT
goes
high, independent of the logic level at
CE
IN
. This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power in-
terruptions. The
LOW LINE
output goes low when V
CC
falls
below the reset threshold.
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
software failure occurs such that WDI not toggled a 200 ms
RESET
pulse will be generated after 1.6 seconds. This typi-
cally restarts the microprocessor’s power-up routine. A new
RESET
pulse is issued every 1.6 seconds until WDI is again
strobed.
The WATCHDOG OUTPUT (
WDO
) goes low if the watch-
dog timer is not serviced within its timeout period. Once
WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI uncon-
nected. OSC IN and OSC SEL also allow other watchdog tim-
ing options.
RESET
also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
The
RESET
output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector
RESET
bus or directly drive a
CMOS gate without an external pullup resistor.
BA3V
0.1μF
0.1μF
OSC IN
OSC SEL
GND
PFI
NC
0.1μF
RESET
WDO
LOW LINE
SINDICATORS
RESET
PFO
WDI
CE
IN
CE
OUT
V
BATT
R2
R1
RAM
DECODE
INPUT POWER
V
CC
BATT
ON
V
OUT
A0–A15
I/O LINE
NMI
RESET
μP
ADM691A
ADM693A
ADM800L
ADM800M
Figure 24. Typical Application Circuit
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