RO 1 RE
參數(shù)資料
型號: ADM483EANZ
廠商: Analog Devices Inc
文件頁數(shù): 13/16頁
文件大?。?/td> 0K
描述: IC TX/RX RS-485 LO-SLEW 5V 8DIP
標(biāo)準(zhǔn)包裝: 50
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
產(chǎn)品目錄頁面: 790 (CN2011-ZH PDF)
ADM483E
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RO 1
RE 2
DE 3
DI 4
VCC
8
B
7
A
6
GND
5
ADM483E
TOP VIEW
(Not to Scale)
0
60
12
-00
2
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RO
Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low.
2
RE
Receiver Output Enable. A low level enables the receiver output, RO. A high level places the receiver output in a high
impedance state.
3
DE
Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places the driver
differential outputs in a high impedance state.
4
DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high. A logic high on DI forces
A high and B low.
5
GND
Ground Connection, 0 V.
6
A
Noninverting Receiver Input A/Driver Output A.
7
B
Inverting Receiver Input B/Driver Output B.
8
VCC
Power Supply, 5 V ± 10%.
Table 5. Selection Table
Part No.
Duplex
Data Rate (kbps)
Low Power Shutdown
Tx/Rx Enable
ICC (μA)
No. of Tx/Rx on Bus
ESD kV
ADM483E
Half
250
Yes
36
32
±15
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參數(shù)描述
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ADM483EAR-REEL 功能描述:IC TX/RX RS-485 LO-SLEW 5V 8SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器,接收器,收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:121 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):1/1 規(guī)程:RS422,RS485 電源電壓:3 V ~ 3.6 V 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-DFN(3x3) 包裝:管件