參數(shù)資料
型號: ADM3101EACPZ
廠商: ANALOG DEVICES INC
元件分類: 通用總線功能
英文描述: Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????)
中文描述: DUAL LINE TRANSCEIVER, QCC12
封裝: 3 X 3 MM, LEAD FREE, LFCSP-12
文件頁數(shù): 8/10頁
文件大?。?/td> 157K
代理商: ADM3101EACPZ
ADM3101E
Preliminary Technical Data
GENERAL DESCRIPTION
The ADM3101E is a single channel RS-232 line driver/receiver.
Step-up voltage converters coupled with level shifting
transmitters and receivers allow RS-232 levels to be developed
while operating from a single 3.3 V supply.
Rev. PrD | Page 8 of 10
CMOS technology is used to keep the power dissipation to an
absolute minimum, allowing maximum battery life in portable
applications.
CIRCUIT DESCRIPTION
The internal circuitry consists of the following main sections:
A charge pump voltage converter
A 3.3 V logic to EIA-232 transmitter
A EIA-232 to 3.3 V logic receiver
Charge Pump DC-DC Voltage Converter
The charge pump voltage converter consists of a 200 kHz
oscillator and a switching matrix. The converter generates a
±6.6 V supply from the input 3.3 V level. This is done in two
stages by using a switched capacitor technique as illustrated in
Figure 12 and Figure 13. First, the 3.3 V input supply is doubled
to 6.6 V by using capacitor C1 as the charge storage element.
The +6.6 V level is then inverted to generate 6.6 V using C2 as
the storage element. C3 is shown connected between V+ and
V
CC
, but is equally effective if connected between V+ and GND.
Capacitors C3 and C4 are used to reduce the output ripple.
Their values are not critical and can be increased, if desired.
Capacitor C3 is shown connected between V+ and V
CC
. It is also
acceptable to connect this capacitor between V+ and GND.
If desired, larger capacitors (up to 10 μF) can be used for
capacitors C1–C4.
C1+
C1-
C2+
C2-
Vcc
V+
V-
T
OUT
R
IN
T
IN
R
OUT
ADM3101E
GND
+3.3V TO +6.6V
Voltage Doubler
+6.6V TO -6.6V
Voltage Inverter
CMOS
Input
CMOS
Output
EIA/TIA-232
Output
EIA/TIA-232
Input*
* Internal 5k
Pull-down resistor
on the RS-232 input
T1
R1
0.1μF
10V
0.1μF
10V
C3
0.1μF
6.3V
C5
0.1μF
C4
0.1μF
10V
+
+
+
+
+
+3.3V Input
Figure 11. ADM3101E Typical Operating Circuit
Figure 12. Charge Pump Voltage Doubler
Figure 13. Charge Pump Voltage Inverter
Transmitter (Driver) Section
The driver convert the 3.3 V logic input levels into RS-232
output levels. With V
CC
= 3.3 V and driving an RS-232 load, the
output voltage swing is typically ±6 V. The T
IN
pin has internally
a weak pull-up which allows it to be driven by an open drain
output, but the maximum operating datarate is reduced when
the T
IN
pin is been driven by a open drain pin.
Receiver Section
The receiver is an inverting level-shifters that accept RS-232
input level and translate it into a 3.3 V logic output level. The
input has an internal 5 k pull-down resistors to ground and is
also protected against overvoltages of up to ±30 V. An
unconnected input is pulled to 0 V by the internal 5 k pull-
down resistor. This, therefore, results in a Logic 1 output level
for an unconnected input or for an input connected to GND.
The receiver has a Schmitt-trigger input with a hysteresis level
of 0.4 V. This ensures error-free reception for both a noisy input
and for an input with slow transition times.
CMOS Input Voltage Thresholds
The ADM3101E CMOS input and output pins (T
IN
and R
OUT
)
are designed to interface with 1.8V logic thresholds when the
ADM3101E’s Vcc = 3.3V.
The ADM3101E CMOS input and output pins (T
IN
and R
OUT
)
are designed to interface with TTL/CMOS logic thresholds
when the ADM3101E’s Vcc = 5V.
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